[Mesa-dev] [PATCH V2 02/22] i965: Choose tiling in brw_miptree_layout() function
Anuj Phogat
anuj.phogat at gmail.com
Fri Apr 24 10:54:18 PDT 2015
On Thu, Apr 23, 2015 at 4:38 PM, Pohjolainen, Topi
<topi.pohjolainen at intel.com> wrote:
> On Fri, Apr 17, 2015 at 04:51:23PM -0700, Anuj Phogat wrote:
>> This refactoring is required by later patches in this series.
>>
>> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
>> ---
>> src/mesa/drivers/dri/i965/brw_tex_layout.c | 19 +++++++++++++++-
>> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 ++++++++++++++-------------
>> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 19 ++++++++++++++--
>> 3 files changed, 51 insertions(+), 18 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
>> index 7a1e09d..b8408d3 100644
>> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
>> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
>> @@ -378,7 +378,13 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
>> }
>>
>> void
>> -brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
>> +brw_miptree_layout(struct brw_context *brw,
>> + mesa_format format,
>> + uint32_t width0,
>> + uint32_t num_samples,
>> + bool for_bo,
>> + enum intel_miptree_tiling_mode requested,
>> + struct intel_mipmap_tree *mt)
>> {
>> bool multisampled = mt->num_samples > 1;
>
> Doesn't given "num_samples" equal to "mt->num_samples", "width0" equal to
> "mt->logical_width0" and "format" equal to "mt->format" at this point?
>
Right. I'll remove them from parameters list.
>> bool gen6_hiz_or_stencil = false;
>> @@ -461,5 +467,16 @@ brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
>> }
>> DBG("%s: %dx%dx%d\n", __FUNCTION__,
>> mt->total_width, mt->total_height, mt->cpp);
>> +
>> + /* pitch == 0 || height == 0 indicates the null texture */
>> + if (!mt || !mt->total_width || !mt->total_height) {
>> + intel_miptree_release(&mt);
>> + return;
>> + }
>> +
>> + if (!for_bo)
>> + mt->tiling = intel_miptree_choose_tiling(brw, format, width0,
>> + num_samples,
>> + requested, mt);
>> }
>>
>> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> index eb226d5..7a64282 100644
>> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
>> @@ -232,6 +232,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>> GLuint depth0,
>> bool for_bo,
>> GLuint num_samples,
>> + enum intel_miptree_tiling_mode requested,
>> bool force_all_slices_at_each_lod)
>> {
>> struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
>> @@ -432,7 +433,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>> if (force_all_slices_at_each_lod)
>> mt->array_layout = ALL_SLICES_AT_EACH_LOD;
>>
>> - brw_miptree_layout(brw, mt);
>> + brw_miptree_layout(brw, format, width0, num_samples, for_bo, requested, mt);
>>
>> return mt;
>> }
>> @@ -440,7 +441,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>> /**
>> * \brief Helper function for intel_miptree_create().
>> */
>> -static uint32_t
>> +uint32_t
>> intel_miptree_choose_tiling(struct brw_context *brw,
>> mesa_format format,
>> uint32_t width0,
>> @@ -609,14 +610,11 @@ intel_miptree_create(struct brw_context *brw,
>> first_level, last_level, width0,
>> height0, depth0,
>> false, num_samples,
>> + requested_tiling,
>
> Just as Matt instructed me, you could fix tabs here in the argument list.
>
OK.
>> force_all_slices_at_each_lod);
>> - /*
>> - * pitch == 0 || height == 0 indicates the null texture
>> - */
>> - if (!mt || !mt->total_width || !mt->total_height) {
>> - intel_miptree_release(&mt);
>> +
>> + if (!mt)
>> return NULL;
>> - }
>>
>> total_width = mt->total_width;
>> total_height = mt->total_height;
>> @@ -627,16 +625,11 @@ intel_miptree_create(struct brw_context *brw,
>> total_height = ALIGN(total_height, 64);
>> }
>>
>> - uint32_t tiling = intel_miptree_choose_tiling(brw, format, width0,
>> - num_samples, requested_tiling,
>> - mt);
>> bool y_or_x = false;
>>
>> - if (tiling == (I915_TILING_Y | I915_TILING_X)) {
>> + if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) {
>> y_or_x = true;
>> mt->tiling = I915_TILING_Y;
>> - } else {
>> - mt->tiling = tiling;
>> }
>>
>> unsigned long pitch;
>> @@ -721,10 +714,18 @@ intel_miptree_create_for_bo(struct brw_context *brw,
>>
>> target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D;
>>
>> + /* 'requested' parameter of intel_miptree_create_layout() is relevant
>> + * only for non bo miptree. Tiling for bo is already computed above.
>> + * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
>> + * just a place holder and will not make any change to the miptree
>> + * tiling format.
>> + */
>> mt = intel_miptree_create_layout(brw, target, format,
>> 0, 0,
>> width, height, depth,
>> - true, 0, false);
>> + true, 0,
>> + INTEL_MIPTREE_TILING_ANY,
>> + false);
>> if (!mt) {
>> free(mt);
>> return mt;
>> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
>> index 41b6036..f03715b 100644
>> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
>> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
>> @@ -540,6 +540,7 @@ intel_miptree_create_layout(struct brw_context *brw,
>> GLuint depth0,
>> bool for_bo,
>> GLuint num_samples,
>> + enum intel_miptree_tiling_mode requested,
>> bool force_all_slices_at_each_lod);
>>
>> struct intel_mipmap_tree *
>> @@ -737,8 +738,14 @@ void
>> intel_miptree_updownsample(struct brw_context *brw,
>> struct intel_mipmap_tree *src,
>> struct intel_mipmap_tree *dst);
>> -
>> -void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt);
>> +void
>> +brw_miptree_layout(struct brw_context *brw,
>> + mesa_format format,
>> + uint32_t width0,
>> + uint32_t num_samples,
>> + bool for_bo,
>> + enum intel_miptree_tiling_mode requested,
>> + struct intel_mipmap_tree *mt);
>>
>> void *intel_miptree_map_raw(struct brw_context *brw,
>> struct intel_mipmap_tree *mt);
>> @@ -765,6 +772,14 @@ intel_miptree_unmap(struct brw_context *brw,
>> unsigned int level,
>> unsigned int slice);
>>
>> +uint32_t
>> +intel_miptree_choose_tiling(struct brw_context *brw,
>> + mesa_format format,
>> + uint32_t width0,
>> + uint32_t num_samples,
>> + enum intel_miptree_tiling_mode requested,
>> + struct intel_mipmap_tree *mt);
>> +
>> void
>> intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
>> unsigned int level, unsigned int layer, enum gen6_hiz_op op);
>> --
>> 2.3.4
>>
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