[Mesa-dev] [PATCH 6/7] i965/cs: Implement brw_emit_gpgpu_walker

[Jordan Justen]

Tested on Ivybridge, Haswell and Broadwell.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_compute.c | 39 ++++++++++++++++++++++++++++++++-
 src/mesa/drivers/dri/i965/brw_defines.h |  1 +
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c b/src/mesa/drivers/dri/i965/brw_compute.c
index baed701..06ef448 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -31,12 +31,49 @@
 #include "brw_draw.h"
 #include "brw_state.h"
 #include "intel_batchbuffer.h"
+#include "brw_defines.h"
 
 
 static void
 brw_emit_gpgpu_walker(struct brw_context *brw, const GLuint *num_groups)
 {
-   _mesa_problem(&brw->ctx, "TODO: implement brw_emit_gpgpu_walker");
+   const struct brw_cs_prog_data *prog_data = brw->cs.prog_data;
+
+   const unsigned simd_size = prog_data->simd_size;
+   unsigned group_size = prog_data->local_size[0] *
+      prog_data->local_size[1] * prog_data->local_size[2];
+   unsigned thread_width_max =
+      (group_size + simd_size - 1) / simd_size;
+
+   uint32_t right_mask = (1u << simd_size) - 1;
+   const unsigned right_non_aligned = group_size & (simd_size - 1);
+   if (right_non_aligned != 0)
+      right_mask >>= (simd_size - right_non_aligned);
+
+   uint32_t dwords = brw->gen < 8 ? 11 : 15;
+   BEGIN_BATCH(dwords);
+   OUT_BATCH(GPGPU_WALKER << 16 | (dwords - 2));
+   OUT_BATCH(0);
+   if (brw->gen >= 8) {
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+   }
+   assert(thread_width_max <= brw->max_cs_threads);
+   OUT_BATCH(((simd_size == 8) ? 0 : 1) << 30 |
+             (thread_width_max - 1));
+   OUT_BATCH(0);
+   if (brw->gen >= 8)
+      OUT_BATCH(0);
+   OUT_BATCH(num_groups[0]);
+   OUT_BATCH(0);
+   if (brw->gen >= 8)
+      OUT_BATCH(0);
+   OUT_BATCH(num_groups[1]);
+   OUT_BATCH(0);
+   OUT_BATCH(num_groups[2]);
+   OUT_BATCH(right_mask);
+   OUT_BATCH(0xffffffff);
+   ADVANCE_BATCH();
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 36f46af..cd25511 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2451,5 +2451,6 @@ enum brw_wm_barycentric_interp_mode {
 
 #define MEDIA_VFE_STATE                         0x7000
 #define MEDIA_INTERFACE_DESCRIPTOR_LOAD         0x7002
+#define GPGPU_WALKER                            0x7105
 
 #endif
-- 
2.1.4