[Mesa-dev] [PATCH 06/21] i965: Add helper function to get a vector component of some register.

[Francisco Jerez]

Define a helper function that returns the vector component of its
argument given by an index (as in, the x/y/z/w components of an actual
GLSL vector).  The purpose is to have a mechanism to do it
consistently across back-ends -- Until now the FS back-end had to use
offset() and the VEC4 back-end had to call swizzle() or writemask()
depending on the register type.
---
 src/mesa/drivers/dri/i965/brw_ir_fs.h   | 13 +++++++++++++
 src/mesa/drivers/dri/i965/brw_ir_vec4.h | 20 ++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 7139934..ee5606f 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -157,6 +157,19 @@ offset(fs_reg reg, unsigned delta)
    return reg;
 }
 
+/**
+ * Return the i-th logical component of register \p reg.  A logical component
+ * is itself a vector with as many channels as the SIMD width of \p reg.  Note
+ * that this happens to be equivalent to offset() in the FS IR because the
+ * number of vector components per addressing unit is one
+ * (cf. fs_reg::traits::chan_size), but that's not in general the case.
+ */
+static inline fs_reg
+component(const fs_reg &reg, unsigned i)
+{
+   return offset(reg, i);
+}
+
 static inline bool
 is_uniform(const fs_reg &reg)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index b52ebb3..f0bdd29 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -95,6 +95,16 @@ negate(src_reg reg)
    return reg;
 }
 
+/**
+ * Return the i-th logical component of register \p reg.  A logical component
+ * is itself a vector with as many channels as the SIMD width of \p reg.
+ */
+static inline src_reg
+component(const src_reg &reg, unsigned i)
+{
+   return swizzle(reg, BRW_SWIZZLE4(i, i, i, i));
+}
+
 static inline bool
 is_uniform(const src_reg &reg)
 {
@@ -149,6 +159,16 @@ writemask(dst_reg reg, unsigned mask)
    return reg;
 }
 
+/**
+ * Return the i-th logical component of register \p reg.  A logical component
+ * is itself a vector with as many channels as the SIMD width of \p reg.
+ */
+static inline dst_reg
+component(const dst_reg &reg, unsigned i)
+{
+   return writemask(reg, 1 << i);
+}
+
 class vec4_instruction : public backend_instruction {
 public:
    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
-- 
2.3.5