[Mesa-dev] [PATCH 07/10] i965/vec4: Get rid of load/store_foo_indirect

Kenneth Graunke kenneth at whitecape.org
Wed Dec 2 00:37:51 PST 2015


On Wednesday, November 25, 2015 09:00:10 PM Jason Ekstrand wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp |  8 +--
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp    | 98 ++++++++++-----------------
>  2 files changed, 40 insertions(+), 66 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
> index 6bc3947..b36f63e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
> @@ -61,19 +61,18 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>     src_reg src;
>  
>     switch (instr->intrinsic) {
> -   case nir_intrinsic_load_per_vertex_input_indirect:
> -      assert(!"EmitNoIndirectInput should prevent this.");
>     case nir_intrinsic_load_per_vertex_input: {
>        /* The EmitNoIndirectInput flag guarantees our vertex index will
>         * be constant.  We should handle indirects someday.
>         */
>        nir_const_value *vertex = nir_src_as_const_value(instr->src[0]);
> +      nir_const_value *offset = nir_src_as_const_value(instr->src[1]);
>  
>        /* Make up a type...we have no way of knowing... */
>        const glsl_type *const type = glsl_type::ivec(instr->num_components);
>  
> -      src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u[0] +
> -                          instr->const_index[0], type);
> +      src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u[0] + offset->u[0],
> +                    type);
>        dest = get_nir_dest(instr->dest, src.type);
>        dest.writemask = brw_writemask_for_size(instr->num_components);
>        emit(MOV(dest, src));
> @@ -81,7 +80,6 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>     }
>  
>     case nir_intrinsic_load_input:
> -   case nir_intrinsic_load_input_indirect:
>        unreachable("nir_lower_io should have produced per_vertex intrinsics");
>  
>     case nir_intrinsic_emit_vertex_with_counter: {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 96787db..2d9461b 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -369,22 +369,16 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>     dst_reg dest;
>     src_reg src;
>  
> -   bool has_indirect = false;
> -
>     switch (instr->intrinsic) {
>  
> -   case nir_intrinsic_load_input_indirect:
> -      has_indirect = true;
> -      /* fallthrough */
>     case nir_intrinsic_load_input: {
> -      int offset = instr->const_index[0];
> -      src = src_reg(ATTR, offset, glsl_type::uvec4_type);
> +      nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
> +
> +      /* We set EmitNoIndirectInput for VS */
> +      assert(const_offset);
> +
> +      src = src_reg(ATTR, const_offset->u[0], glsl_type::uvec4_type);
>  
> -      if (has_indirect) {
> -         dest.reladdr = new(mem_ctx) src_reg(get_nir_src(instr->src[0],
> -                                                         BRW_REGISTER_TYPE_D,
> -                                                         1));
> -      }
>        dest = get_nir_dest(instr->dest, src.type);
>        dest.writemask = brw_writemask_for_size(instr->num_components);
>  
> @@ -392,22 +386,16 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>        break;
>     }
>  
> -   case nir_intrinsic_store_output_indirect:
> -      has_indirect = true;
> -      /* fallthrough */
>     case nir_intrinsic_store_output: {
> -      int varying = instr->const_index[0];
> +      nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
> +      assert(const_offset);
> +
> +      int varying = const_offset->u[0];
>  
>        src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
>                          instr->num_components);
> -      dest = dst_reg(src);
>  
> -      if (has_indirect) {
> -         dest.reladdr = new(mem_ctx) src_reg(get_nir_src(instr->src[1],
> -                                                         BRW_REGISTER_TYPE_D,
> -                                                         1));
> -      }
> -      output_reg[varying] = dest;
> +      output_reg[varying] = dst_reg(src);
>        break;
>     }
>  
> @@ -437,9 +425,6 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>        break;
>     }
>  
> -   case nir_intrinsic_store_ssbo_indirect:
> -      has_indirect = true;
> -      /* fallthrough */
>     case nir_intrinsic_store_ssbo: {
>        assert(devinfo->gen >= 7);
>  
> @@ -464,20 +449,19 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>        }
>  
>        /* Offset */
> -      src_reg offset_reg = src_reg(this, glsl_type::uint_type);
> -      unsigned const_offset_bytes = 0;
> -      if (has_indirect) {
> -         emit(MOV(dst_reg(offset_reg), get_nir_src(instr->src[2], 1)));
> +      src_reg offset_reg;
> +      nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
> +      if (const_offset) {
> +         offset_reg = brw_imm_ud(const_offset->u[0]);
>        } else {
> -         const_offset_bytes = instr->const_index[0];
> -         emit(MOV(dst_reg(offset_reg), brw_imm_ud(const_offset_bytes)));
> +         offset_reg = get_nir_src(instr->src[2], 1);
>        }
>  
>        /* Value */
>        src_reg val_reg = get_nir_src(instr->src[0], 4);
>  
>        /* Writemask */
> -      unsigned write_mask = instr->const_index[1];
> +      unsigned write_mask = instr->const_index[0];
>  
>        /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
>         * writes will use SIMD8 mode. In order to hide this and keep symmetry across
> @@ -543,9 +527,8 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>                  * write at to skip the channels we skipped, if any.
>                  */
>                 if (skipped_channels > 0) {
> -                  if (!has_indirect) {
> -                     const_offset_bytes += 4 * skipped_channels;
> -                     offset_reg = brw_imm_ud(const_offset_bytes);
> +                  if (offset_reg.file == BRW_IMMEDIATE_VALUE) {

offset_reg.file == IMM please.
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