[Mesa-dev] [PATCH 3/3] winsys/amdgpu: addrlib - port a Fiji bug fix

[Marek Olšák]

From: Sonny Jiang <sonny.jiang at amd.com>

Fiji: Fixed tiled resource failures

Change-Id: Idbad4c09ded6dd5cb28d6342f9b04a3345377c82
Signed-off-by: Sonny Jiang <sonny.jiang at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
---
 .../winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp   | 45 +++++++++++++++++++++-
 .../winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h     |  2 +
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
index 7393953..995f276 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
@@ -896,6 +896,49 @@ BOOL_32 CIAddrLib::HwlOverrideTileMode(
 
 /**
 ***************************************************************************************************
+*   CiAddrLib::GetPrtSwitchP4Threshold
+*
+*   @brief
+*       Return the threshold of switching to P4_* instead of P16_* for PRT resources
+***************************************************************************************************
+*/
+UINT_32 CiAddrLib::GetPrtSwitchP4Threshold() const
+{
+    UINT_32 threshold;
+
+    switch (m_pipes)
+    {
+        case 8:
+            threshold = 32;
+            break;
+        case 16:
+            if (m_settings.isFiji)
+            {
+                threshold = 16;
+            }
+            else if (m_settings.isHawaii)
+            {
+                threshold = 8;
+            }
+            else
+            {
+                ///@todo add for possible new ASICs.
+                ADDR_ASSERT_ALWAYS();
+                threshold = 16;
+            }
+            break;
+        default:
+            ///@todo add for possible new ASICs.
+            ADDR_ASSERT_ALWAYS();
+            threshold = 32;
+            break;
+    }
+
+    return threshold;
+}
+
+/**
+***************************************************************************************************
 *   CIAddrLib::HwlSetupTileInfo
 *
 *   @brief
@@ -1123,7 +1166,7 @@ VOID CIAddrLib::HwlSetupTileInfo(
             {
                 UINT_32 bytesXSamples = bpp * numSamples / 8;
                 UINT_32 bytesXThickness = bpp * thickness / 8;
-                UINT_32 switchP4Threshold = (m_pipes == 16) ? 8 : 32;
+                UINT_32 switchP4Threshold = GetPrtSwitchP4Threshold();
 
                 if ((bytesXSamples > switchP4Threshold) || (bytesXThickness > switchP4Threshold))
                 {
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
index 4515086..4cbe970 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
@@ -167,6 +167,8 @@ private:
     VOID ReadGbMacroTileCfg(
         UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
 
+    UINT_32 GetPrtSwitchP4Threshold() const;
+
     BOOL_32 InitTileSettingTable(
         const UINT_32 *pSetting, UINT_32 noOfEntries);
 
-- 
2.1.4