[Mesa-dev] [PATCH 2/3] winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible

[Marek Olšák]

From: Sonny Jiang <sonny.jiang at amd.com>

Change-Id: I3a6ae6b76b13aa95103f68ca3a2a8d03d5d0aeb1
Signed-off-by: Sonny Jiang <sonny.jiang at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
---
 src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp | 4 +++-
 src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h   | 3 ++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
index 110e3d0..088b645 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.cpp
@@ -352,6 +352,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
     ComputeSurfaceAlignmentsMicroTiled(expTileMode,
                                        pIn->bpp,
                                        pIn->flags,
+                                       pIn->mipLevel,
                                        numSamples,
                                        &pOut->baseAlign,
                                        &pOut->pitchAlign,
@@ -647,6 +648,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
     AddrTileMode        tileMode,          ///< [in] tile mode
     UINT_32             bpp,               ///< [in] bits per pixel
     ADDR_SURFACE_FLAGS  flags,             ///< [in] surface flags
+    UINT_32             mipLevel,          ///< [in] mip level
     UINT_32             numSamples,        ///< [in] number of samples
     UINT_32*            pBaseAlign,        ///< [out] base address alignment in bytes
     UINT_32*            pPitchAlign,       ///< [out] pitch alignment in pixels
@@ -669,7 +671,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
     // ECR#393489
     // Workaround 2 for 1D tiling -  There is HW bug for Carrizo
     // where it requires the following alignments for 1D tiling.
-    if (flags.czDispCompatible)
+    if (flags.czDispCompatible && (mipLevel == 0))
     {
         *pBaseAlign  = PowTwoAlign(*pBaseAlign, 4096);                         //Base address MOD 4096 = 0
         *pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
index 84adb66..25e3896 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/egbaddrlib.h
@@ -315,7 +315,8 @@ private:
         UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
 
     BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
-        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
+        AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
+        UINT_32 mipLevel, UINT_32 numSamples,
         UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
 
     BOOL_32 ComputeSurfaceAlignmentsMacroTiled(
-- 
2.1.4