[Mesa-dev] [PATCH 1/7] i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge

[Jason Ekstrand]

Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on
vec4-aligned byte offsets on Iron Lake and below and worked in terms of
vec4 offsets on Sandy Bridge.  On Ivy Bridge, we add a new *LOAD_GEN7
variant which works in terms of vec4s.  We're about to change the GEN7
version to work in terms of bytes, so this is a nice unification.
---
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 +++++++++++++++--
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp       | 18 +++++++++++++-----
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   |  6 +++---
 3 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 434c4dc..c3426dd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -903,8 +903,21 @@ generate_pull_constant_load(struct brw_codegen *p,
 
    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 
-   brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
-	   offset);
+   if (devinfo->gen >= 6) {
+      if (offset.file == BRW_IMMEDIATE_VALUE) {
+         brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
+                           BRW_REGISTER_TYPE_D),
+                 brw_imm_d(offset.ud >> 4));
+      } else {
+         brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
+                           BRW_REGISTER_TYPE_D),
+                 offset, brw_imm_d(4));
+      }
+   } else {
+      brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
+                        BRW_REGISTER_TYPE_D),
+              offset);
+   }
 
    uint32_t msg_type;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 1e03022..80925f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -759,12 +759,20 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
       unsigned const_offset = instr->const_index[0];
       src_reg offset;
 
-      if (!has_indirect)  {
-         offset = brw_imm_ud(const_offset / 16);
+      if (devinfo->gen <= 6) {
+         if (!has_indirect)  {
+            offset = brw_imm_ud(const_offset & ~15);
+         } else {
+            offset = get_nir_src(instr->src[1], nir_type_int, 1);
+         }
       } else {
-         offset = src_reg(this, glsl_type::uint_type);
-         emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
-                  brw_imm_ud(4u)));
+         if (!has_indirect)  {
+            offset = brw_imm_ud(const_offset / 16);
+         } else {
+            offset = src_reg(this, glsl_type::uint_type);
+            emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
+                     brw_imm_ud(4u)));
+         }
       }
 
       src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index b1e5398..36b8933 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1474,10 +1474,10 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
       emit_before(block, inst, ADD(dst_reg(index), *reladdr,
                                    brw_imm_d(reg_offset)));
 
-      /* Pre-gen6, the message header uses byte offsets instead of vec4
+      /* Pre-gen7, the message header uses byte offsets instead of vec4
        * (16-byte) offset units.
        */
-      if (devinfo->gen < 6) {
+      if (devinfo->gen < 7) {
          emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
       }
 
@@ -1488,7 +1488,7 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
       emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset)));
       return offset;
    } else {
-      int message_header_scale = devinfo->gen < 6 ? 16 : 1;
+      int message_header_scale = devinfo->gen < 7 ? 16 : 1;
       return brw_imm_d(reg_offset * message_header_scale);
    }
 }
-- 
2.5.0.400.gff86faf