[Mesa-dev] [PATCH 4/5] i965/gen9: Don't change halign and valign to fit in fast copy blit
Anuj Phogat
anuj.phogat at gmail.com
Fri Dec 11 19:14:23 PST 2015
Changing the suggested alignmnet caused piglit regressions. halign and
valign fields in fast copy blit are not used anyways. See more details
in a later patch.
Cc: Chad Versace <chad.versace at intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index a294829..530fe2d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -765,8 +765,8 @@ intel_miptree_set_alignment(struct brw_context *brw,
} else if (brw->gen >= 9 && mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE) {
/* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32 or
* vertical alignment < 64. */
- mt->halign = MAX2(tr_mode_horizontal_texture_alignment(mt), 32);
- mt->valign = MAX2(tr_mode_vertical_texture_alignment(mt), 64);
+ mt->halign = tr_mode_horizontal_texture_alignment(mt);
+ mt->valign = tr_mode_vertical_texture_alignment(mt);
} else {
mt->halign =
intel_horizontal_texture_alignment_unit(brw, mt, layout_flags);
--
2.5.0
More information about the mesa-dev
mailing list