[Mesa-dev] [PATCH 5/5] i965/gen9: Remove the halign/valign field setup code in fast copy blit

[Anuj Phogat]

Experimentation with different values for src/dst horizontal/vertical
alignment showed that these fileds are not used on gen9 hardware.
So, this patch removes the code to setup those fields. A bug has been
created to get the spec language corrected.

Note: Setting up these fields isn't hurting on SKL. So, I'm also
fine with leaving them as it is until we see the corrections in
h/w spec.

Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Chad Versace <chad.versace at intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/intel_blit.c | 70 +++-------------------------------
 1 file changed, 6 insertions(+), 64 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 6d29fbd..5ebc988 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -104,64 +104,6 @@ br13_for_cpp(int cpp)
    }
 }
 
-static uint32_t
-get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
-   /* Alignment tables for YF/YS tiled surfaces. */
-   const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16};
-   const uint32_t bpp = cpp * 8;
-   const uint32_t shift = is_src ? 17 : 10;
-   uint32_t align;
-   int i = 0;
-
-   if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
-      return 0;
-
-   /* Compute array index. */
-   assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
-   i = ffs(bpp / 8) - 1;
-
-   align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
-           align_2d_yf[i] :
-           4 * align_2d_yf[i];
-
-   assert(_mesa_is_pow_two(align));
-
-   /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
-   if (align == 16)
-      align = 32;
-
-   return (ffs(align) - 6) << shift;
-}
-
-static uint32_t
-get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
-   /* Vertical alignment tables for YF/YS tiled surfaces. */
-   const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
-   const uint32_t bpp = cpp * 8;
-   const uint32_t shift = is_src ? 15 : 8;
-   uint32_t align;
-   int i = 0;
-
-   if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
-      return 0;
-
-   /* Compute array index. */
-   assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
-   i = ffs(bpp / 8) - 1;
-
-   align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
-           align_2d_yf[i] :
-           4 * align_2d_yf[i];
-
-   assert(_mesa_is_pow_two(align));
-
-   /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
-   if (align == 16 || align == 32)
-      align = 64;
-
-   return (ffs(align) - 7) << shift;
-}
-
 /**
  * Emits the packet for switching the blitter from X to Y tiled or back.
  *
@@ -458,12 +400,12 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
       if (src_tiling != I915_TILING_NONE)
          SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
 
-      CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */);
-      CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */);
-
-      CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */);
-      CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */);
-
+      /* NOTE: Horizontal and vertical alignment fields for src and dst are
+       * not used by XY_FAST_COPY_BLT in gen9. So, the code to setup those
+       * fields has been removed. We may want that code back for future
+       * generations of hardware. A bug has been created to get the
+       * language in h/w spec corrected.
+       */
    } else {
       assert(cpp <= 4);
       switch (cpp) {
-- 
2.5.0