[Mesa-dev] [PATCH] i965: Add tr_mode and mip tail information in surface state dump
Anuj Phogat
anuj.phogat at gmail.com
Wed Dec 23 13:31:48 PST 2015
On Wed, Dec 23, 2015 at 1:12 PM, Ben Widawsky <ben at bwidawsk.net> wrote:
> On Wed, Dec 23, 2015 at 12:09:44PM -0800, Anuj Phogat wrote:
> > Cc: Ben Widawsky <ben at bwidawsk.net>
> > Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> > ---
> > src/mesa/drivers/dri/i965/brw_state_dump.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
> b/src/mesa/drivers/dri/i965/brw_state_dump.c
> > index 3d3a6cf..facd4dc 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state_dump.c
> > +++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
> > @@ -319,10 +319,13 @@ dump_gen8_surface_state(struct brw_context *brw,
> uint32_t offset, int index)
> > GET_FIELD(surf[4], GEN7_SURFACE_MIN_ARRAY_ELEMENT),
> > GET_FIELD(surf[4], GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT)
> + 1,
> > 1 << GET_BITS(surf[4], 5, 3));
> > - batch_out(brw, name, offset, 5, "x,y offset: %d,%d, min LOD: %d\n",
> > + batch_out(brw, name, offset, 5, "x,y offset: %d,%d, min LOD: %d,"
> > + " tr_mode: %d, mip tail: %d\n",
> > GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
> > GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET),
> > - GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD));
> > + GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD),
> > + GET_FIELD(surf[5], GEN9_SURFACE_TRMODE),
> > + GET_FIELD(surf[5], GEN9_SURFACE_MIP_TAIL_START_LOD));
> > batch_out(brw, name, offset, 6, "AUX pitch: %d qpitch: %d\n",
> > GET_FIELD(surf[6], GEN8_SURFACE_AUX_QPITCH) << 2,
> > GET_FIELD(surf[6], GEN8_SURFACE_AUX_PITCH) << 2);
>
> Should be gen9 only... I don't think it's quite time yet to bother
> splitting out
> gen9 surface state, but maybe add "(gen9+)" to the actual print and then
> it's:
> Reviewed-by: Ben Widawsky <benjamin.widawsky at intel.com>
>
I'll add "(gen9+)".
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