[Mesa-dev] [PATCH 4/6] i965: Don't force x-tiling for 16-bpp formats on Gen>7
neil at linux.intel.com
Fri Feb 20 14:31:06 PST 2015
Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.
This is important to do for Skylake which doesn't support x-tiling for
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0e3888f..994670a 100644
@@ -516,9 +516,9 @@ intel_miptree_choose_tiling(struct brw_context *brw,
* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
* or Linear."
* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
- * all the way back to 965, but is explicitly permitted on Gen7.
+ * all the way back to 965, but is explicitly permitted on Gen7+.
- if (brw->gen != 7 && mt->cpp >= 16)
+ if (brw->gen < 7 && mt->cpp >= 16)
/* From the Ivy Bridge PRM, Vol4 Part1 126.96.36.199 (SURFACE_STATE for most
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