[Mesa-dev] [PATCH 4/6] i965: Don't force x-tiling for 16-bpp formats on Gen>7

[Ben Widawsky]

On Fri, Feb 20, 2015 at 10:31:06PM +0000, Neil Roberts wrote:
> Sandybridge doesn't support y-tiling for surface formats with 16 or
> more bpp. There was previously an override to explicitly allow this
> for Gen7. However, this restriction is also removed in Gen8+ so we
> should use y-tiling there too.
> 
> This is important to do for Skylake which doesn't support x-tiling for
> 3D surfaces.
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 0e3888f..994670a 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -516,9 +516,9 @@ intel_miptree_choose_tiling(struct brw_context *brw,
>      * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
>      *  or Linear."
>      * 128 bits per pixel translates to 16 bytes per pixel.  This is necessary
> -    * all the way back to 965, but is explicitly permitted on Gen7.
> +    * all the way back to 965, but is explicitly permitted on Gen7+.
>      */
> -   if (brw->gen != 7 && mt->cpp >= 16)
> +   if (brw->gen < 7 && mt->cpp >= 16)
>        return I915_TILING_X;
>  
>     /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most

I had this same patch somewhere, but it looks like I never sent it out. (I'd get
rid of the "explicitly" in the comment, but up to you.)

Reviewed-by: Ben Widawsky <ben at bwidawsk.net>