[Mesa-dev] [PATCH 10/14] i965: Make a function to check the conditions to use the blitter
Neil Roberts
neil at linux.intel.com
Tue Feb 24 08:35:55 PST 2015
Anuj Phogat <anuj.phogat at gmail.com> writes:
> No functional changes in the patch. Just makes the code look cleaner.
>
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +++++++++++++++++++--------
> 1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index abf20c9..147097b 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2305,6 +2305,34 @@ can_blit_slice(struct intel_mipmap_tree *mt,
> return true;
> }
>
> +static bool
> +use_intel_mipree_map_blit(struct brw_context *brw,
> + struct intel_mipmap_tree *mt,
> + GLbitfield mode,
> + unsigned int level,
> + unsigned int slice)
> +{
> + if (brw->has_llc &&
> + /* It's probably not worth swapping to the blit ring because of
> + * all the overhead involved.
> + */
> + !(mode & GL_MAP_WRITE_BIT) &&
> + !mt->compressed &&
> + (mt->tiling == I915_TILING_X ||
> + /* Prior to Sandybridge, the blitter can't handle Y tiling */
> + (brw->gen >= 6 && mt->tiling == I915_TILING_Y)) &&
This line used to have an extra space of indentation in the old version
which made it clearer that it is inside the brackets above. I think the
space should be added back here.
The patch is an improvement so I think it's worth landing but I wonder
if now that's in a separate function it might be worth tidying it up a
bit to make the logic easier to follow.
Either way, if the space is added back then it is
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Regards,
- Neil
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