[Mesa-dev] [PATCH 4/4] i965: Force miptrees for BOs to have all slices in each lod.

[Laura Ekstrand]

Ken and I discussed doing this only for when mt->first_layer ==
mt->last_layer
and decided to try this instead.  In testing, it didn't seem to impact
other platforms (I used jenkins).

Still, after poking at this again today and talking with Jason, I think
that the best long term solution is to send a v2 such as you suggested
where I eliminate any chance that the user will try to create an array
texture for the pbo in meta_texsubimage.  This will most likely involve
reverting commits such as 404660e.

As far as this particular patch is concerned, since it doesn't actually fix
a known issue, let's discard it for now.

On Mon, Feb 23, 2015 at 11:57 AM, Neil Roberts <neil at linux.intel.com> wrote:

> Is this patch no longer relevant considering the earlier patches make it
> no longer use array textures?
>
> Otherwise, does this work for gens other than 7? If I've understood the
> bspec correctly, only Gen7 has the surface array spacing option in the
> surface state so it's not possible to choose this layout on other gens.
> I think on Gen6 this layout gets chosen for you depending on certain
> circumstances. On Gen8+ you can get the same benefit as this layout by
> just picking your own qpitch value that doesn't include space for the
> mipmaps. I have posted a patch for Skylake which effectively implements
> this by using mt->total_height for the qpitch value as this will either
> have space for the mipmaps or not depending on the values of
> mt->first_level and mt->last_level.
>
> http://lists.freedesktop.org/archives/mesa-dev/2015-February/077607.html
>
> We might want to do something like your patch for Gen7 but in
> intel_miptree_create_layout instead of intel_miptree_create_for_bo. We
> can make it pick the ALL_SLICES_AT_EACH_LOD layout whenever
> mt->first_level==mt->last_level in addition to the other cases where it
> is chosen.
>
> For Gen8 I think setting that will magically make it pick a qpitch value
> that will make it work, but it'd be a bit weird because it won't really
> be using the ALL_SLICES_AT_EACH_LOD layout and it will only be correct
> if there are no mipmaps. Instead it might be better to handle it
> directly when picking the qpitch value like the Skylake patch.
>
> Regards,
> - Neil
>
> Laura Ekstrand <laura at jlekstrand.net> writes:
>
> > Textures made expressly for internal buffer objects shouldn't have extra
> > padding around them, but should be densely packed.
> > ---
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 0e3888f..b46532d 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -724,7 +724,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
> >     mt = intel_miptree_create_layout(brw, target, format,
> >                                      0, 0,
> >                                      width, height, depth,
> > -                                    true, 0, false);
> > +                                    true, 0, true);
> >     if (!mt) {
> >        free(mt);
> >        return mt;
> > --
> > 2.1.0
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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