[Mesa-dev] [PATCH 1/4] i965: Rename some PIPE_CONTROL flags

Kristian Høgsberg krh at bitplanet.net
Fri Feb 27 10:32:26 PST 2015


On Fri, Feb 27, 2015 at 10:22 AM, Ben Widawsky
<benjamin.widawsky at intel.com> wrote:
> I'm not really sure of the origins of the existing flag names. Modern docs have
> some slightly different names. Having the correct names makes it easier to
> determine if existing PIPE_CONTROL flag settings are correct, as well as making
> adding new PIPE_CONTROLs easier.
>
> This originally came up while I was trying to implement workarounds and spotted
> some things called, "flush" which should have been called "invalidate."

Yeah, good point.

Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>

> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/brw_program.c       | 10 +++++-----
>  src/mesa/drivers/dri/i965/gen6_vs_state.c     |  2 +-
>  src/mesa/drivers/dri/i965/gen8_depth_state.c  |  2 +-
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c |  8 ++++----
>  src/mesa/drivers/dri/i965/intel_reg.h         |  6 +++---
>  5 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
> index aed595e..70b5a62 100644
> --- a/src/mesa/drivers/dri/i965/brw_program.c
> +++ b/src/mesa/drivers/dri/i965/brw_program.c
> @@ -195,24 +195,24 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
>        bits |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
>
>     if (barriers & GL_UNIFORM_BARRIER_BIT)
> -      bits |= (PIPE_CONTROL_TC_FLUSH |
> +      bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                 PIPE_CONTROL_CONST_CACHE_INVALIDATE);
>
>     if (barriers & GL_TEXTURE_FETCH_BARRIER_BIT)
> -      bits |= PIPE_CONTROL_TC_FLUSH;
> +      bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
>
>     if (barriers & GL_TEXTURE_UPDATE_BARRIER_BIT)
> -      bits |= PIPE_CONTROL_WRITE_FLUSH;
> +      bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
>
>     if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
>        bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> -               PIPE_CONTROL_WRITE_FLUSH);
> +               PIPE_CONTROL_RENDER_TARGET_FLUSH);
>
>     /* Typed surface messages are handled by the render cache on IVB, so we
>      * need to flush it too.
>      */
>     if (brw->gen == 7 && !brw->is_haswell)
> -      bits |= PIPE_CONTROL_WRITE_FLUSH;
> +      bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
>
>     brw_emit_pipe_control_flush(brw, bits);
>  }
> diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> index ee68ba5..35d10ef 100644
> --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> @@ -248,7 +248,7 @@ upload_vs_state(struct brw_context *brw)
>      */
>     brw_emit_pipe_control_flush(brw,
>                                 PIPE_CONTROL_DEPTH_STALL |
> -                               PIPE_CONTROL_INSTRUCTION_FLUSH |
> +                               PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>                                 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
>  }
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> index b4eb6e1..5c56d51 100644
> --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> @@ -340,7 +340,7 @@ write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
>      * Flush is also necessary.
>      */
>     const uint32_t render_cache_flush =
> -      ctx->Stencil._WriteEnabled ? PIPE_CONTROL_WRITE_FLUSH : 0;
> +      ctx->Stencil._WriteEnabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
>     brw_emit_pipe_control_flush(brw,
>                                 PIPE_CONTROL_CS_STALL |
>                                 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 7b96005..f19406f 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -411,7 +411,7 @@ intel_batchbuffer_data(struct brw_context *brw,
>  static void
>  gen8_add_cs_stall_workaround_bits(uint32_t *flags)
>  {
> -   uint32_t wa_bits = PIPE_CONTROL_WRITE_FLUSH |
> +   uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
>                        PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                        PIPE_CONTROL_WRITE_IMMEDIATE |
>                        PIPE_CONTROL_WRITE_DEPTH_COUNT |
> @@ -665,7 +665,7 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
>        OUT_BATCH(0);
>        ADVANCE_BATCH();
>     } else {
> -      int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_WRITE_FLUSH;
> +      int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
>        if (brw->gen >= 6) {
>           if (brw->gen == 9) {
>              /* Hardware workaround: SKL
> @@ -676,10 +676,10 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw)
>              brw_emit_pipe_control_flush(brw, 0);
>           }
>
> -         flags |= PIPE_CONTROL_INSTRUCTION_FLUSH |
> +         flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                    PIPE_CONTROL_VF_CACHE_INVALIDATE |
> -                  PIPE_CONTROL_TC_FLUSH |
> +                  PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
>                    PIPE_CONTROL_CS_STALL;
>
>           if (brw->gen == 6) {
> diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
> index a4bcf3d..488fb5b 100644
> --- a/src/mesa/drivers/dri/i965/intel_reg.h
> +++ b/src/mesa/drivers/dri/i965/intel_reg.h
> @@ -64,9 +64,9 @@
>  #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
>  #define PIPE_CONTROL_WRITE_TIMESTAMP   (3 << 14)
>  #define PIPE_CONTROL_DEPTH_STALL       (1 << 13)
> -#define PIPE_CONTROL_WRITE_FLUSH       (1 << 12)
> -#define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11)
> -#define PIPE_CONTROL_TC_FLUSH          (1 << 10) /* GM45+ only */
> +#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
> +#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
> +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE  (1 << 10) /* GM45+ only */
>  #define PIPE_CONTROL_ISP_DIS           (1 << 9)
>  #define PIPE_CONTROL_INTERRUPT_ENABLE  (1 << 8)
>  /* GT */
> --
> 2.3.1
>
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