[Mesa-dev] [PATCH 2/4] i965: Add more stringent blitter assertions

[Jason Ekstrand]

First two are
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

On Tue, Jan 13, 2015 at 11:37 PM, Ben Widawsky <benjamin.widawsky at intel.com>
wrote:

> Blits to or from a y-tiled surface must always be a multiple of the tile
> size.
> From page 16 of the HSW PRM
> (
> https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16
> )
> "The pitch of a tiled enclosing region must be an integral number of tile
> widths"
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/intel_blit.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index e919528..9500bd7 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -307,6 +307,9 @@ intelEmitCopyBlit(struct brw_context *brw,
>     if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
>        return false;
>
> +   assert(!dst_y_tiled || (dst_pitch % 128) == 0);
> +   assert(!src_y_tiled || (src_pitch % 128) == 0);
> +
>     /* do space check before going any further */
>     do {
>         aper_array[0] = brw->batch.bo;
> --
> 2.2.1
>
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