[Mesa-dev] [PATCH v2 30/82] i965: Use 16-byte offset alignment for shader storage buffers

[Jordan Justen]

30-32 Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

On 2015-06-03 00:01:20, Iago Toral Quiroga wrote:
> This is the same we do for other things like uniforms because it ensures
> optimal performance.
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
> index 274a237..5d21747 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -544,6 +544,7 @@ brw_initialize_context_constants(struct brw_context *brw)
>      * However, unaligned accesses are slower, so enforce buffer alignment.
>      */
>     ctx->Const.UniformBufferOffsetAlignment = 16;
> +   ctx->Const.ShaderStorageBufferOffsetAlignment = 16;
>     ctx->Const.TextureBufferOffsetAlignment = 16;
>  
>     if (brw->gen >= 6) {
> -- 
> 1.9.1
> 
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