[Mesa-dev] [PATCH v3 (part2) 01/56] i965: Use 16-byte offset alignment for shader storage buffers

[Iago Toral Quiroga]

This is the same we do for other things like uniforms because it ensures
optimal performance.

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 8150b94..d92d7c2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -546,6 +546,7 @@ brw_initialize_context_constants(struct brw_context *brw)
     * However, unaligned accesses are slower, so enforce buffer alignment.
     */
    ctx->Const.UniformBufferOffsetAlignment = 16;
+   ctx->Const.ShaderStorageBufferOffsetAlignment = 16;
    ctx->Const.TextureBufferOffsetAlignment = 16;
    ctx->Const.MaxTextureBufferSize = 128 * 1024 * 1024;
 
-- 
1.9.1