[Mesa-dev] [PATCH v2 0/6] Improvements to the vec4 spilling code

Iago Toral Quiroga itoral at igalia.com
Tue Jul 28 03:24:45 PDT 2015

Link to v1:

Changes after review (Curro)
  - Drop the patch that asserted that the reg size should always be 1
  - Expand this so that we do not unspill a register if we have just
    unspilled it as well
  - Use brw_mask_for_swizzle
  - Update spilling costs accordingly

New changes:

  - Expand the optimizations that are based on caching the spilled/unspilled
    so we keep using the cached register for as long as consecutive instructions
    keep reading the register (the previous version would only do this for one
    instruction). This is because we only see benefits for register allocation
    when there are gaps in the life span of a register where it is not used
    (because these are the only instances in which we can use that reg for a
    different purpose), so as long as consecutive instructions keep reading a
    register we have just spilled or unspilled, we don't have to unspill it

Iago Toral Quiroga (6):
  i965/vec4: Only emit one scratch read per instruction for spilled
  i965/vec4: Remove checks for reladdr when checking for spillable
  i965/vec4: Don't emit scratch reads for a spilled register we have
    just written
  i965/vec4: Don't emit scratch reads for a register we have just
  i965/vec4: Adjust spilling cost for consecutive instructions
  i965: Add a debug option for spilling everything in vec4 code

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp  |   2 +-
 src/mesa/drivers/dri/i965/brw_vec4.cpp             |   2 +-
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     | 145 +++++++++++++++++++--
 src/mesa/drivers/dri/i965/intel_debug.c            |   3 +-
 src/mesa/drivers/dri/i965/intel_debug.h            |   5 +-
 5 files changed, 139 insertions(+), 18 deletions(-)


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