[Mesa-dev] [PATCH resend 7/7] i965: Disable HW-binding tables on batch finish for Broadwell

[Abdiel Janulgue]

This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated binding tables
when done using it in the batch. Otherwise the GPU would no longer
accept software binding tables submitted by other clients including
but not limited to the Xorg driver.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 11 +++++++++++
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |  3 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index caeb31b..4244cab 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -33,6 +33,7 @@
 #include "intel_fbo.h"
 #include "brw_context.h"
 #include "brw_state.h"
+#include "brw_defines.h"
 
 #include <xf86drm.h>
 #include <i915_drm.h>
@@ -337,6 +338,7 @@ _intel_batchbuffer_flush(struct brw_context *brw,
 			 const char *file, int line)
 {
    int ret;
+   struct intel_batchbuffer *batch = &brw->batch;
 
    if (brw->batch.used == 0)
       return 0;
@@ -361,6 +363,15 @@ _intel_batchbuffer_flush(struct brw_context *brw,
 
    brw_finish_batch(brw);
 
+   if (brw->has_resource_streamer && brw->gen >=8 && batch->ring != BLT_RING) {
+      intel_batchbuffer_emit_dword(brw,
+                                   _3DSTATE_BINDING_TABLE_POOL_ALLOC << 16 |
+                                   (4 - 2));
+      intel_batchbuffer_emit_dword(brw, 0);
+      intel_batchbuffer_emit_dword(brw, 0);
+      intel_batchbuffer_emit_dword(brw, 0);
+   }
+
    /* Mark the end of the buffer. */
    intel_batchbuffer_emit_dword(brw, MI_BATCH_BUFFER_END);
    if (brw->batch.used & 1) {
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 7bdd836..0a8ad7f 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -26,8 +26,9 @@ extern "C" {
  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  *       Sandybridge PIPE_CONTROL madness.
+ *     - 4 Dwords for disabling RS on batch end ==> 16 bytes
  */
-#define BATCH_RESERVED 146
+#define BATCH_RESERVED 162
 
 struct intel_batchbuffer;
 
-- 
1.9.1