[Mesa-dev] [RFC v2 11/15] i965: change the meaning of cpp for compressed textures
Nanley Chery
nanleychery at gmail.com
Mon Jun 1 10:13:49 PDT 2015
From: Nanley Chery <nanley.g.chery at intel.com>
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Along with changing the cpp definition, the units for miptree_level x_offset
and miptree total_width has changed in 2d miptrees from pixels to number of
blocks (for the given format).
A new macro ROUND_UP_TO is added (from libdrm) that performs the same operation
as ALIGN, but does not require the alignment value to be a power of two (as is
the case when working with ASTC values).
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 13 +++++++------
src/mesa/drivers/dri/i965/intel_copy_image.c | 12 ------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +---------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
src/mesa/main/macros.h | 12 ++++++++++++
5 files changed, 21 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 72b02a2..dacaad7 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -215,7 +215,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
mt->total_width = mt->physical_width0;
if (mt->compressed) {
- mt->total_width = ALIGN(mt->physical_width0, mt->align_w);
+ mt->total_width = ROUND_UP_TO(mt->physical_width0, mt->align_w);
}
/* May need to adjust width to accommodate the placement of
@@ -227,10 +227,10 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
unsigned mip1_width;
if (mt->compressed) {
- mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
- ALIGN(minify(mt->physical_width0, 2), bw);
+ mip1_width = ROUND_UP_TO(minify(mt->physical_width0, 1), mt->align_w) +
+ ROUND_UP_TO(minify(mt->physical_width0, 2), bw);
} else {
- mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
+ mip1_width = ROUND_UP_TO(minify(mt->physical_width0, 1), mt->align_w) +
minify(mt->physical_width0, 2);
}
@@ -239,6 +239,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
}
+ mt->total_width /= bw;
mt->total_height = 0;
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
@@ -246,7 +247,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
intel_miptree_set_level_info(mt, level, x, y, depth);
- img_height = ALIGN(height, mt->align_h);
+ img_height = ROUND_UP_TO(height, mt->align_h);
if (mt->compressed)
img_height /= bh;
@@ -263,7 +264,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
/* Layout_below: step right after second mipmap.
*/
if (level == mt->first_level + 1) {
- x += ALIGN(width, mt->align_w);
+ x += ROUND_UP_TO(width, mt->align_w) / bw;
} else {
y += img_height;
}
diff --git a/src/mesa/drivers/dri/i965/intel_copy_image.c b/src/mesa/drivers/dri/i965/intel_copy_image.c
index f4c7eff..9193be5 100644
--- a/src/mesa/drivers/dri/i965/intel_copy_image.c
+++ b/src/mesa/drivers/dri/i965/intel_copy_image.c
@@ -87,12 +87,6 @@ copy_image_with_blitter(struct brw_context *brw,
src_width /= (int)bw;
src_height /= (int)bh;
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- src_image_x /= bw;
-
cpp = _mesa_get_format_bytes(src_mt->format);
} else {
cpp = src_mt->cpp;
@@ -111,12 +105,6 @@ copy_image_with_blitter(struct brw_context *brw,
dst_x /= (int)bw;
dst_y /= (int)bh;
-
- /* Inside of the miptree, the x offsets are stored in pixels while
- * the y offsets are stored in blocks. We need to scale just the x
- * offset.
- */
- dst_image_x /= bw;
}
dst_x += dst_image_x;
dst_y += dst_image_y;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 24a5c3d..48bacdb 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -288,15 +288,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
mt->disable_aux_buffers = disable_aux_buffers;
exec_list_make_empty(&mt->hiz_map);
-
- /* The cpp is bytes per (1, blockheight)-sized block for compressed
- * textures. This is why you'll see divides by blockheight all over
- */
- unsigned bw, bh;
- _mesa_get_format_block_size(format, &bw, &bh);
- assert(_mesa_get_format_bytes(mt->format) % bw == 0);
- mt->cpp = _mesa_get_format_bytes(mt->format) / bw;
-
+ mt->cpp = _mesa_get_format_bytes(format);
mt->num_samples = num_samples;
mt->compressed = _mesa_is_format_compressed(format);
mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 8b42e4a..b0fd78a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -382,7 +382,7 @@ struct intel_mipmap_tree
*/
GLuint physical_width0, physical_height0, physical_depth0;
- GLuint cpp; /**< bytes per pixel */
+ GLuint cpp; /**< bytes per pixel (or bytes per block if compressed) */
GLuint num_samples;
bool compressed;
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index 0608650..c794da3 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -715,6 +715,18 @@ is_power_of_two(unsigned value)
*/
#define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
+/**
+ * Align a value up to an alignment value
+ *
+ * If \c value is not already aligned to the requested alignment value, it
+ * will be rounded up.
+ *
+ * \param value Value to be rounded
+ * \param alignment Alignment value to be used.
+ *
+ * \sa ALIGN()
+ */
+#define ROUND_UP_TO(value, alignment) (((value) + (alignment) - 1) / (alignment) * (alignment))
/** Cross product of two 3-element vectors */
static inline void
--
2.4.1
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