[Mesa-dev] [PATCH] i965/fs: Use UW-typed immediate in multiply inst.

[Chris Forbes]

After discussion on IRC, this seems reasonable to me. Unfortunate that
CHV is fussy.

Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>

On Wed, Jun 3, 2015 at 1:24 PM, Matt Turner <mattst88 at gmail.com> wrote:
> Some hardware reads only the low 16-bits even if the type is UD, but
> other hardware like Cherryview can't handle this.
>
> Fixes spec at arb_gpu_shader5@execution at sampler_array_indexing@fs-simple on
> Cherryview.
> ---
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 40a3db3..ff05b2a 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -788,7 +788,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
>        brw_set_default_access_mode(p, BRW_ALIGN_1);
>
>        /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
> -      brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
> +      brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
>        if (base_binding_table_index)
>           brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
>        brw_AND(p, addr, addr, brw_imm_ud(0xfff));
> --
> 2.3.6
>
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