[Mesa-dev] [PATCH 04/16] drirc: add the macros necessary to share options across all the drivers
Martin Peres
martin.peres at linux.intel.com
Fri Jun 5 06:03:58 PDT 2015
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
---
src/gallium/state_trackers/dri/dri_screen.c | 7 +++++++
src/mesa/drivers/dri/common/xmlpool.h | 12 ++++++++++++
src/mesa/drivers/dri/i915/intel_screen.c | 7 +++++++
src/mesa/drivers/dri/i965/intel_screen.c | 7 +++++++
src/mesa/drivers/dri/nouveau/nouveau_context.c | 16 +++++++++++++++-
src/mesa/drivers/dri/radeon/radeon_screen.c | 12 ++++++++++++
src/mesa/drivers/dri/swrast/swrast.c | 16 +++++++++++++++-
7 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/dri/dri_screen.c b/src/gallium/state_trackers/dri/dri_screen.c
index 08affdd..74efae7 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -53,7 +53,12 @@ const __DRIconfigOptionsExtension gallium_config_options = {
.xml =
DRI_CONF_BEGIN
+ DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
+ DRI_CONF_SECTION_END
+
DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_PP_CELSHADE(0)
DRI_CONF_PP_NORED(0)
@@ -64,6 +69,7 @@ const __DRIconfigOptionsExtension gallium_config_options = {
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN("false")
DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS("false")
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
@@ -73,6 +79,7 @@ const __DRIconfigOptionsExtension gallium_config_options = {
DRI_CONF_SECTION_END
DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER("false")
DRI_CONF_SECTION_END
DRI_CONF_END
diff --git a/src/mesa/drivers/dri/common/xmlpool.h b/src/mesa/drivers/dri/common/xmlpool.h
index ebd4e7c..010eee9 100644
--- a/src/mesa/drivers/dri/common/xmlpool.h
+++ b/src/mesa/drivers/dri/common/xmlpool.h
@@ -102,4 +102,16 @@
*/
#include "xmlpool/options.h"
+#define DRI_CONF_SECTION_PERFORMANCE_SHARED \
+ "<!-- No shared performance options yet -->\n"
+
+#define DRI_CONF_SECTION_QUALITY_SHARED \
+ "<!-- No shared quality options yet -->\n"
+
+#define DRI_CONF_SECTION_DEBUG_SHARED \
+ "<!-- No shared debug options yet -->\n"
+
+#define DRI_CONF_SECTION_MISC_SHARED \
+ "<!-- No shared msic options yet -->\n"
+
#endif
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c
index 77af328..a96020f 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -47,6 +47,7 @@ static const __DRIconfigOptionsExtension i915_config_options = {
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC)
/* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
* DRI_CONF_BO_REUSE_ALL
@@ -64,9 +65,11 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
@@ -79,6 +82,10 @@ DRI_CONF_BEGIN
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 896a125..a99761a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -48,6 +48,7 @@ static const __DRIconfigOptionsExtension brw_config_options = {
.xml =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_ALWAYS_SYNC)
/* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
* DRI_CONF_BO_REUSE_ALL
@@ -65,6 +66,7 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
DRI_CONF_FORCE_S3TC_ENABLE("false")
DRI_CONF_OPT_BEGIN(clamp_max_samples, int, -1)
@@ -74,6 +76,7 @@ DRI_CONF_BEGIN
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
DRI_CONF_NO_RAST("false")
DRI_CONF_ALWAYS_FLUSH_BATCH("false")
DRI_CONF_ALWAYS_FLUSH_CACHE("false")
@@ -87,6 +90,10 @@ DRI_CONF_BEGIN
DRI_CONF_DESC(en, "Perform code generation at shader link time.")
DRI_CONF_OPT_END
DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index f7773a2..8a05230 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -55,7 +55,21 @@ static const __DRIconfigOptionsExtension nouveau_vieux_config_options = {
.xml =
DRI_CONF_BEGIN
- /* will be filled later with cross-driver options */
+ DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 45d9b2b..887fb6c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -76,6 +76,7 @@ static const __DRIconfigOptionsExtension radeon_config_options = {
.xml =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
@@ -84,6 +85,7 @@ DRI_CONF_BEGIN
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS("false")
@@ -93,8 +95,12 @@ DRI_CONF_BEGIN
DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
DRI_CONF_NO_RAST("false")
DRI_CONF_SECTION_END
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
@@ -104,6 +110,7 @@ static const __DRIconfigOptionsExtension radeon_config_options = {
.xml =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
@@ -112,6 +119,7 @@ DRI_CONF_BEGIN
DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
DRI_CONF_NO_NEG_LOD_BIAS("false")
@@ -122,8 +130,12 @@ DRI_CONF_BEGIN
DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
DRI_CONF_NO_RAST("false")
DRI_CONF_SECTION_END
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
#endif
diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c
index 1819445..f7d317f 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -73,7 +73,21 @@ static const __DRIconfigOptionsExtension swrast_config_options = {
.xml =
DRI_CONF_BEGIN
- /* will be filled later with cross-driver options */
+ DRI_CONF_SECTION_PERFORMANCE
+ DRI_CONF_SECTION_PERFORMANCE_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_QUALITY
+ DRI_CONF_SECTION_QUALITY_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_DEBUG
+ DRI_CONF_SECTION_DEBUG_SHARED
+ DRI_CONF_SECTION_END
+
+ DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_SECTION_MISC_SHARED
+ DRI_CONF_SECTION_END
DRI_CONF_END
};
--
2.4.2
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