[Mesa-dev] [PATCH 5/6] i965/gen9: Set HALIGN_16 for all aux buffers

[Ben Widawsky]

Just like the previous patch, but for the GEN9 constraints.

v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Cc: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4d3b9ab..203515c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -488,10 +488,25 @@ intel_miptree_create_layout(struct brw_context *brw,
    if (layout_flags & MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD)
       mt->array_layout = ALL_SLICES_AT_EACH_LOD;
 
-   /* Use HALIGN_16 if MCS is enabled for non-MSRT */
-   if (brw->gen >= 8 && num_samples < 2 &&
-       intel_miptree_is_fast_clear_capable(brw, mt))
+   /*
+    * Obey HALIGN_16 constraints for Gen8 and Gen9.
+    *
+    * GEN  |    MSRT      |      AUX
+    *  ----------------------------------
+    *  9   |  HALIGN_16   |    HALIGN_16
+    *  8   |  HALIGN_ANY  |    HALIGN_16
+    *  7   |  HALIGN_ANY  |    HALIGN_ANY
+    *  6   |  HALIGN_ANY  |     INVALID
+    */
+   if (intel_miptree_is_fast_clear_capable(brw, mt)) {
+      if (brw->gen >= 9 || (brw->gen == 8 && num_samples == 1))
+         layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+   } else if (brw->gen >= 9 && num_samples > 1) {
       layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16;
+   } else {
+      /* For now, nothing else has this requirement */
+      assert((layout_flags & MIPTREE_LAYOUT_FORCE_HALIGN16) == 0);
+   }
 
    brw_miptree_layout(brw, mt, layout_flags);
 
@@ -671,6 +686,7 @@ intel_miptree_create(struct brw_context *brw,
 
    assert((layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) == 0);
    assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0);
+
    mt = intel_miptree_create_layout(brw, target, format,
                                     first_level, last_level, width0,
                                     height0, depth0, num_samples,
-- 
2.4.2