[Mesa-dev] [PATCH 6/6] i965/gen8+: Add aux buffer alignment assertions

[Ben Widawsky]

This helped find the incorrect HALIGN values from the previous patches.

Since this patch adds the asserts, I thought it was a good place for the series'
piglit results:
http://otc-mesa-ci.jf.intel.com/view/dev/job/bwidawsk/lastSuccessfulBuild/

v2: Add PRM references for assertions (Chad)

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
---
 src/mesa/drivers/dri/i965/gen8_surface_state.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 672fc70..84aa734 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -178,6 +178,17 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
    if (mt->mcs_mt) {
       aux_mt = mt->mcs_mt;
       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+
+      /*
+       * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
+       * "When MCS is enabled for non- * MSRT, HALIGN_16 must be used"
+       *
+       * From the hardware spec for GEN9: uoting the hardware spec for gen9:
+       * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
+       *  16 must be used."
+       */
+      assert(brw->gen < 9 || mt->align_w == 16);
+      assert(brw->gen < 8 || mt->num_samples > 0 || mt->align_w == 16);
    }
 
    uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
@@ -391,6 +402,17 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    if (mt->mcs_mt) {
       aux_mt = mt->mcs_mt;
       aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+
+      /*
+       * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
+       * "When MCS is enabled for non- * MSRT, HALIGN_16 must be used"
+       *
+       * From the hardware spec for GEN9: uoting the hardware spec for gen9:
+       * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
+       *  16 must be used."
+       */
+      assert(brw->gen < 9 || mt->align_w == 16);
+      assert(brw->gen < 8 || mt->num_samples > 0 || mt->align_w == 16);
    }
 
    uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
-- 
2.4.2