[Mesa-dev] [v4 PATCH 08/10] i965: execution of frag-shader when it has atomic buffer

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

On 05/27/2015 02:49 AM, Kevin Rogovin wrote:
> Ensure that the GPU spawns the fragment shader thread for those
> fragment shaders with atomic buffer access.
> 
> v2:
>  No change.
> 
> v3:
>  Use utility function _mesa_active_fragment_shader_has_atomic_ops().
> 
> v4:
>  Formatting fixes.
> 
> Reviewed-by: Tapani Pälli <tapani.palli at intel.com> (v1)
> Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 ++++
>  src/mesa/drivers/dri/i965/gen8_ps_state.c | 3 +++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> index 1c47076..ea11ae8 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> @@ -77,6 +77,10 @@ upload_wm_state(struct brw_context *brw)
>        dw1 |= GEN7_WM_KILL_ENABLE;
>     }
>  
> +   if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx)) {
> +      dw1 |= GEN7_WM_DISPATCH_ENABLE;
> +   }
> +
>     /* _NEW_BUFFERS | _NEW_COLOR */
>     if (brw_color_buffer_write_enabled(brw) || writes_depth ||
>         dw1 & GEN7_WM_KILL_ENABLE) {
> diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> index 85ad3b6..b9cae50 100644
> --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> @@ -58,6 +58,9 @@ gen8_upload_ps_extra(struct brw_context *brw,
>     if (prog_data->uses_omask)
>        dw1 |= GEN8_PSX_OMASK_TO_RENDER_TARGET;
>  
> +   if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx))
> +      dw1 |= GEN8_PSX_SHADER_HAS_UAV;
> +
>     BEGIN_BATCH(2);
>     OUT_BATCH(_3DSTATE_PS_EXTRA << 16 | (2 - 2));
>     OUT_BATCH(dw1);
>