[Mesa-dev] [PATCH] nir: Allow vec2/vec3/vec4 instructions in the select peephole pass.
Kenneth Graunke
kenneth at whitecape.org
Wed Jun 10 02:55:40 PDT 2015
These are basically just moves, so they should be safe as well.
When disabling i965's GLSL IR level scalarizer (channel expressions)
pass, I started seeing NIR code like this:
if ssa_21 {
block block_1:
/* preds: block_0 */
vec4 ssa_120 = vec4 ssa_82, ssa_83, ssa_84, ssa_30
/* succs: block_3 */
} else {
block block_2:
/* preds: block_0 */
/* succs: block_3 */
}
block block_3:
/* preds: block_1 block_2 */
vec4 ssa_33 = phi block_1: ssa_120, block_2: ssa_2
Previously, the GLSL IR scalarizer pass would break the vec4 into a
series of fmovs, which were allowed by the peephole pass. But with
the vec4 operation, they were not. We want to keep getting selects.
Normal i965 on Broadwell:
instructions in affected programs: 200 -> 176 (-12.00%)
helped: 4
With brw_fs_channel_expressions() disabled:
instructions in affected programs: 1832 -> 1646 (-10.15%)
helped: 30
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/glsl/nir/nir_opt_peephole_select.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_opt_peephole_select.c b/src/glsl/nir/nir_opt_peephole_select.c
index 82c65bb..ef7c977 100644
--- a/src/glsl/nir/nir_opt_peephole_select.c
+++ b/src/glsl/nir/nir_opt_peephole_select.c
@@ -86,7 +86,9 @@ block_check_for_allowed_instrs(nir_block *block)
nir_alu_instr *mov = nir_instr_as_alu(instr);
if (mov->op != nir_op_fmov && mov->op != nir_op_imov &&
mov->op != nir_op_fneg && mov->op != nir_op_ineg &&
- mov->op != nir_op_fabs && mov->op != nir_op_iabs)
+ mov->op != nir_op_fabs && mov->op != nir_op_iabs &&
+ mov->op != nir_op_vec2 && mov->op != nir_op_vec3 &&
+ mov->op != nir_op_vec4)
return false;
/* Can't handle saturate */
--
2.4.2
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