[Mesa-dev] [PATCH 2/2] i965/vec4: Fix the source register for indexed samplers
Neil Roberts
neil at linux.intel.com
Wed Jun 10 07:02:17 PDT 2015
Previously when setting up the sample instruction for an indirect
sampler the vec4 backend was directly passing the pseudo opcode's
src0. However vec4_visitor::visit(ir_texture *) doesn't set the
texture operation's src0 -- it's left as BAD_FILE, which when
translated into a brw_reg gives the null register. In brw_SAMPLE,
gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and
sets the src0 appropriately. The indirect sampler case did not have a
call to gen6_resolve_implied_move().
The fs backend avoids this because the platforms that support dynamic
indexing of samplers (IVB+) have been converted to not use the
fake-MRF hack, and instead send from proper GRFs.
This patch makes it call gen6_resolve_implied_move in
brw_send_indirect_surface_message so that it matches what is done in
brw_SAMPLE. To make this work the base_mrf needs to be passed into the
function. This is only relevant for texture sampling from the vec4
backend because I think all of the other cases that call it would use
send the message from a GRF as the function only works on Gen7+
anyway. The rest of the places that call it just pass -1.
The Piglit tests for sampler array indexing didn't pick this up
because they were using a texture with a solid colour so it didn't
matter what texture coordinates were actually used. I've posted a
patch for Piglit to make the tests more thorough here:
http://lists.freedesktop.org/archives/piglit/2015-May/016127.html
With that patch the tests for gs and vs are currently failing on
Ivybridge, but this patch fixes them. There are no other changes to a
Piglit run on Ivybridge.
On Skylake the gs tests were failing even without the Piglit patch
because Skylake needs the source registers to work correctly in order
to send a message header to select SIMD4x2 mode.
(The explanation in the commit message is partially written by Matt
Turner)
---
src/mesa/drivers/dri/i965/brw_eu.h | 1 +
src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 +++++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 4 ++--
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 0e7be1e..1580715 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -251,6 +251,7 @@ struct brw_inst *
brw_send_indirect_message(struct brw_codegen *p,
unsigned sfid,
struct brw_reg dst,
+ unsigned msr_reg_nr,
struct brw_reg payload,
struct brw_reg desc);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index a1d11f3..6059488 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2487,6 +2487,7 @@ struct brw_inst *
brw_send_indirect_message(struct brw_codegen *p,
unsigned sfid,
struct brw_reg dst,
+ unsigned msg_reg_nr,
struct brw_reg payload,
struct brw_reg desc)
{
@@ -2495,6 +2496,9 @@ brw_send_indirect_message(struct brw_codegen *p,
assert(desc.type == BRW_REGISTER_TYPE_UD);
+ if (msg_reg_nr != -1)
+ gen6_resolve_implied_move(p, &payload, msg_reg_nr);
+
if (desc.file == BRW_IMMEDIATE_VALUE) {
setup = send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src1(p, send, desc);
@@ -2560,7 +2564,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
surface = addr;
}
- insn = brw_send_indirect_message(p, sfid, dst, payload, surface);
+ insn = brw_send_indirect_message(p, sfid, dst, -1, payload, surface);
brw_inst_set_mlen(devinfo, insn, message_len);
brw_inst_set_rlen(devinfo, insn, response_len);
brw_inst_set_header_present(devinfo, insn, header_present);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ff05b2a..e2556a1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -797,7 +797,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
- p, BRW_SFID_SAMPLER, dst, src, addr);
+ p, BRW_SFID_SAMPLER, dst, inst->base_mrf, src, addr);
brw_set_sampler_message(p, insn,
0 /* surface */,
0 /* sampler */,
@@ -1121,7 +1121,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
/* dst = send(payload, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
- p, BRW_SFID_SAMPLER, dst, src, addr);
+ p, BRW_SFID_SAMPLER, dst, inst->base_mrf, src, addr);
brw_set_sampler_message(p, insn,
0,
0, /* LD message ignores sampler unit */
@@ -1272,7 +1272,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
- offset, addr);
+ inst->base_mrf, offset, addr);
brw_set_sampler_message(p, insn,
0 /* surface */,
0 /* sampler */,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 67495d2..80fa92e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -416,7 +416,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
- p, BRW_SFID_SAMPLER, dst, src, addr);
+ p, BRW_SFID_SAMPLER, dst, inst->base_mrf, src, addr);
brw_set_sampler_message(p, insn,
0 /* surface */,
0 /* sampler */,
@@ -1068,7 +1068,7 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
- p, BRW_SFID_SAMPLER, dst, offset, addr);
+ p, BRW_SFID_SAMPLER, dst, inst->base_mrf, offset, addr);
brw_set_sampler_message(p, insn,
0 /* surface */,
0 /* sampler */,
--
1.9.3
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