[Mesa-dev] [PATCH] i965: correct alignment units for 2D compressed textures on Skylake

[Nanley Chery]

From: Nanley Chery <nanley.g.chery at intel.com>

On Gen9+, vertical and horizontal alignment values for compressed textures are
equal to the pre-Gen9 value squared. Each miplevel must be aligned to this
value.

Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
---

This fixes an FXT1 Piglit test regression and shows no failures on Jenkins. 

 src/mesa/drivers/dri/i965/brw_tex_layout.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 312a887..dffc699 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -149,15 +149,8 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
       unsigned int i, j;
       _mesa_get_format_block_size(mt->format, &i, &j);
 
-      /* On Gen9+ we can pick our own alignment for compressed textures but it
-       * has to be a multiple of the block size. The minimum alignment we can
-       * pick is 4 so we effectively have to align to 4 times the block
-       * size
-       */
-      if (brw->gen >= 9)
-         return i * 4;
-      else
-         return i;
+      /* On Gen9+ the alignment value is squared. */
+      return brw->gen >= 9 ? i * i : i;
     }
 
    if (mt->format == MESA_FORMAT_S_UINT8)
@@ -269,9 +262,12 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
     * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
     * the SURFACE_STATE "Surface Vertical Alignment" field.
     */
-   if (_mesa_is_format_compressed(mt->format))
+   if (_mesa_is_format_compressed(mt->format)) {
+      unsigned int i, j;
+      _mesa_get_format_block_size(mt->format, &i, &j);
       /* See comment above for the horizontal alignment */
-      return brw->gen >= 9 ? 16 : 4;
+      return brw->gen >= 9 ? j * j : j;
+   }
 
    if (mt->format == MESA_FORMAT_S_UINT8)
       return brw->gen >= 7 ? 8 : 4;
@@ -379,7 +375,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 
        if (mt->compressed) {
           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
-             ALIGN(minify(mt->physical_width0, 2), bw);
+             ALIGN(minify(mt->physical_width0, 2), mt->align_w);
        } else {
           mip1_width = ALIGN(minify(mt->physical_width0, 1), mt->align_w) +
              minify(mt->physical_width0, 2);
-- 
2.4.2