[Mesa-dev] [PATCH] i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()

[Tapani Pälli]

Alignment restriction is for _mm_stream_load_si128 used by 
_mesa_streaming_load_memcpy

("The 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the 
instruction will cause a #GP.")

Reviewed-by: Tapani Pälli <tapani.palli at intel.com>

On 06/11/2015 02:50 AM, Anuj Phogat wrote:
> I don't know where this alignment restriction came from. We have an
> assert() in intel_miptree_map_movntdqa() which expects the pitch to
> be 16 byte aligned.
>
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> ---
>   src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index d4d9e76..b0b2697 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2659,7 +2659,9 @@ intel_miptree_map(struct brw_context *brw,
>      } else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
>         intel_miptree_map_blit(brw, mt, map, level, slice);
>   #if defined(USE_SSE41)
> -   } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
> +   } else if (!(mode & GL_MAP_WRITE_BIT) &&
> +              !mt->compressed && cpu_has_sse4_1 &&
> +              (mt->pitch % 16 == 0)) {
>         intel_miptree_map_movntdqa(brw, mt, map, level, slice);
>   #endif
>      } else {
>