[Mesa-dev] [PATCH] i965: Fix aligning to the block size in intel_miptree_copy_slice

[Nanley Chery]

Hey Neil,

While this patch does fix FXT1, it also regresses 21 other Piglit tests on SKL.

- Nanley

On Thu, Jun 11, 2015 at 8:59 AM, Neil Roberts <neil at linux.intel.com> wrote:
> This function was trying to align the width and height to a multiple
> of the block size for compressed textures. It was using align_w/h as a
> shortcut to get the block size as up until Gen9 this always happens to
> match. However in Gen9+ the alignment values are expressed as
> multiples of the block size so in effect the alignment values are
> always 4 for compressed textures as that is the minimum value we can
> pick. This happened to work for most compressed formats because the
> block size is also 4, but for FXT1 this was breaking because it has a
> block width of 8.
>
> This fixes some Piglit tests testing FXT1 such as
>
> spec at 3dfx_texture_compression_fxt1@fbo-generatemipmap-formats
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 615cbfb..6c00581 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1168,8 +1168,10 @@ intel_miptree_copy_slice(struct brw_context *brw,
>     assert(src_mt->format == dst_mt->format);
>
>     if (dst_mt->compressed) {
> -      height = ALIGN(height, dst_mt->align_h) / dst_mt->align_h;
> -      width = ALIGN(width, dst_mt->align_w);
> +      unsigned int i, j;
> +      _mesa_get_format_block_size(dst_mt->format, &i, &j);
> +      height = ALIGN(height, j) / j;
> +      width = ALIGN(width, i);
>     }
>
>     /* If it's a packed depth/stencil buffer with separate stencil, the blit
> --
> 1.9.3
>
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