[Mesa-dev] [PATCH] i965: correct alignment units for 2D compressed textures on Skylake

[Nanley Chery]

>>>
>>>  src/mesa/drivers/dri/i965/brw_tex_layout.c | 20 ++++++++------------
>>>  1 file changed, 8 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
>>> index 312a887..dffc699 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
>>> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
>>> @@ -149,15 +149,8 @@ intel_horizontal_texture_alignment_unit(struct brw_context *brw,
>>>        unsigned int i, j;
>>>        _mesa_get_format_block_size(mt->format, &i, &j);
>>>
>>> -      /* On Gen9+ we can pick our own alignment for compressed textures but it
>>> -       * has to be a multiple of the block size. The minimum alignment we can
>>> -       * pick is 4 so we effectively have to align to 4 times the block
>>> -       * size
>>> -       */
>>> -      if (brw->gen >= 9)
>>> -         return i * 4;
>>> -      else
>>> -         return i;
>>> +      /* On Gen9+ the alignment value is squared. */
>>> +      return brw->gen >= 9 ? i * i : i;
>>
>> I don't think this is right. Isn't this going to push non compressed textures to
>> an invalid HALIGN when we divide later ie. don't you get 1?
>>
> The divide only occurs for compressed textures.
>
Sorry, this isn't quite right. The divide occurs for all textures, but
the divisor is the block size. For non compressed textures, it will be
1.

-Nanley