[Mesa-dev] [PATCH] nir: add helper to get # of src/dest components

Rob Clark robdclark at gmail.com
Fri Jun 19 16:20:45 PDT 2015

On Fri, Jun 19, 2015 at 6:45 PM, Connor Abbott <cwabbott0 at gmail.com> wrote:
> On Thu, Jun 18, 2015 at 12:04 PM, Rob Clark <robdclark at gmail.com> wrote:
>> It is only vaguely an issue at the moment
>> because the priority-queue scheduler that replaced what is on master
>> does very badly with wide/shallow shaders, ie. like
>> glsl-fs-convolution-1... ie. shaders with a lot of instructions at
>> minimum depth.. (but I have some ideas to fix that)
> P.S. what does your heuristic currently look like? I was working on
> i965 scheduling, and after some discussion, this is what I did:
> http://cgit.freedesktop.org/~cwabbott0/mesa/commit/?h=i965-sched&id=2d46e424327082bbc67758d05e6e102cbcd56d89
> it's called "delay" in that code for some reason instead of "depth"
> (or, even better, critical path length), but you should get the
> idea... choose the earliest thing we can schedule, and then among
> those pick the thing with the largest depth.

current heuristic is just depth.  But if we have a large # of
instructions with depth==1 those end up getting scheduled first
increasing the register pressure..

(although on thinking about it, seems like I have something backwards,
maybe I end up taking from the head of the depth sorted list instead
of tail..  I should check that.. I hadn't really spent any time at all
playing w/ the heuristic yet.. I just noticed that glsl-fs-convolution
was a good example case of where I end up doing badly at the moment)


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