[Mesa-dev] [PATCH] i965/gen9: use an unreserved surface alignment value

[Anuj Phogat]

On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery <nanleychery at gmail.com> wrote:
> From: Nanley Chery <nanley.g.chery at intel.com>
>
> Although the horizontal and vertical alignment fields are ignored here,
> 0 is a reserved value for them and may cause undefined behavior. Change
> the default value to an abitrary valid one.
>
> Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index b2d1a57..22ae960 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -93,7 +93,7 @@ vertical_alignment(const struct brw_context *brw,
>     if (brw->gen > 8 &&
>         (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
>          surf_type == BRW_SURFACE_1D))
> -      return 0;
> +      return GEN8_SURFACE_VALIGN_4;
>
>     switch (mt->align_h) {
>     case 4:
> @@ -118,7 +118,7 @@ horizontal_alignment(const struct brw_context *brw,
>     if (brw->gen > 8 &&
>         (mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
>          gen9_use_linear_1d_layout(brw, mt)))
> -      return 0;
> +      return GEN8_SURFACE_HALIGN_4;
>
>     switch (mt->align_w) {
>     case 4:
> --
> 2.4.4
>
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Good find Nanley. We had no known issues with value 0 but it's
always nice to avoid undefined behavior :).

Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>