[Mesa-dev] [PATCH v2 05/19] i965/fs: Explicitly set the exec_size on the add(32) in interpolation setup

[Jason Ekstrand]

Soon we will start using the builder to explicitly set all the execution
sizes.  We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption.  Sinc this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.

Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>

v2: Explicitly new the fs_inst instead of using the builder and setting
    exec_size after the fact.

v3: Set force_writemask_all with the builder instead of directly.  The
    builder over-writes it if we set it manually.  Also, if we don't have
    force_writemask_all in the builder it will assert-fail on SIMD32.
---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 9a4bad6..8976c25 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1357,10 +1357,12 @@ fs_visitor::emit_interpolation_setup_gen6()
        */
       fs_reg int_pixel_xy(GRF, alloc.allocate(dispatch_width / 8),
                           BRW_REGISTER_TYPE_UW, dispatch_width * 2);
-      abld.exec_all()
-          .ADD(int_pixel_xy,
-               fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
-               fs_reg(brw_imm_v(0x11001010)));
+      fs_inst *add =
+         new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dispatch_width * 2,
+                               int_pixel_xy,
+                               fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
+                               fs_reg(brw_imm_v(0x11001010)));
+      abld.exec_all().emit(add);
 
       this->pixel_x = vgrf(glsl_type::float_type);
       this->pixel_y = vgrf(glsl_type::float_type);
-- 
2.4.3