[Mesa-dev] [PATCH 00/78] i965: A new vec4 backend based on NIR
Eduardo Lima Mitev
elima at igalia.com
Fri Jun 26 01:06:16 PDT 2015
Hello,
This series adds a new vec4 backend for i965 based on NIR. It is the result of working on
https://bugs.freedesktop.org/show_bug.cgi?id=89580.
This backend is activated if all the following conditions are met:
* INTEL_USE_NIR environment variable is set to 1 (or true)
* The stage is a GLSL vertex shader (the pass does not support geometry shaders or ARB_vertex_program yet)
* Hardware is gen6 or gen7 (specifically, we tested on SNB, IVB and HSW)
Otherwise the backend is disabled and the usual vec4_visitor is used.
The backend implementation is heavily based on vec4_visitor, and it is in fact part of that class. However we have taken care to make the new backend as much self-contained as possible, to ease an eventual removal of the vec4_visitor path. For dealing with NIR data-structures, we heavily borrowed ideas and patterns from the fs_nir backend.
At the moment, the backend shows no piglit regressions on SNB, IVB and HSW. There is one piglit test that fails in master but crashes on our backend. The test uses multiple indirect indexings on an expression with sampler arrays, which is expected to hit an assertion in NIR when --enable-debug autoconf flag is set.
The backend shows no functional dEQP regressions. On HSW and IVB, however, there are some particularly heavy tests (~80) that fail at link time due to register spilling, which should be fixed once optimization work on the backend is done.
People interested in trying the backend can use this git tree (and remember to have INTEL_USE_NIR=1):
$ git clone -b nir-vec4-v1 https://github.com/Igalia/mesa.git
The structure of the patch set is:
The first patch (0001) adds the main structure of the backend, with placeholders for each main functionality.
The second patch (0002) adds logic to select between the current vec4_visitor pass, and the new NIR->vec4 pass.
The rest of the patches incrementally fill placeholders with atomic functionality. In some cases, the division might seem arbitrary (i.e, nir_emit_texture(), which is basically one method), but we decided to favor having more atomic patches to facilitate review, and maybe squash the patches just before merging.
cheers,
Eduardo
Alejandro Piñeiro (12):
i965/vec4: Overload make_reg_for_system_value() to allow reuse in
NIR->vec4 pass
i965/nir/vec4: Add setup for system values
i965/nir/vec4: Implement intrinsics that load system values
i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)
i965/nir: Disable alu_to_scalar pass on non-scalar shaders
i965/nir/vec4: Add skeleton implementation of nir_emit_texture()
i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type
i965/nir/vec4: Implement loading of nir_tex_src_comparitor
i965/nir/vec4: Implement loading of nir_tex_src_coord
i965/nir/vec4: Setup LOD source register
i965/nir/vec4: Implement nir_texop_tex and nir_texop_txl texture ops
i965/nir/vec4: Implement nir_texop_txf texture op
Antia Puentes (33):
i965/nir/vec4: Implement loading values from an UBO
i965/nir/vec4: Prepare source and destination registers for ALU
operations
i965/nir/vec4: Implement single-element "mov" operations
i965/nir/vec4: Lower "vecN" instructions and mark them unreachable
i965/nir/vec4: Implement int<->float format conversion ops
i965/nir/vec4: Implement the addition operation
i965/nir/vec4: Implement multiplication
i965/vec4: Return the last emitted instruction in emit_math()
i965/nir/vec4: Implement more math operations
i965/nir/vec4: Implement carry/borrow for addition/subtraction
i965/nir/vec4: Implement float-related functions
i965/vec4: Return the emitted instruction in emit_minmax()
i965/nir/vec4: Implement min/max operations
i965/nir/vec4: Derivatives are not allowed in VS
i965/nir: Add utility method for comparisons
i965/nir/vec4: Implement non-vector comparison ops
i965/nir/vec4: Add swizzle utility method for vector ops
i965/nir/vec4: Implement equality ops on vectors
i965/nir/vec4: Implement non-equality ops on vectors
i965/nir/vec4: Implement logical operators
i965/nir/vec4: Implement "bool<->int,float" format conversion
i965/nir/vec4: "noise" ops should already be lowered
i965/nir/vec4: Implement pack/unpack operations
i965/nir/vec4: Implement bit operations
i965/nir/vec4: Implement the "sign" operation
i965/nir/vec4: Implement "shift" operations
i965/nir/vec4: Implement floating-point fused multiply-add
i965/vec4: Return the emitted instruction in emit_lrp()
i965/nir/vec4: Implement linear interpolation
i965/nir/vec4: Implement conditional select
i965/nir/vec4: Implement the dot product operation
i965/nir/vec4: Implement vector "any" operation
i965/nir/vec4: Mark as unreachable ops that should be already lowered
Eduardo Lima Mitev (26):
i965/nir/vec4: Add implementation placeholders for a new NIR->vec4
pass
i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor
code-paths
i965/vec4: Move type_size() method to brw_vec4_visitor class
i965/nir/vec4: Add setup of input variables in NIR->vec4 pass
i965/nir/vec4: Add setup of output variables in NIR->vec4 pass
i965/nir/vec4: Add shader function implementation
i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse
i965/vec4: Add auxiliary func to build a writemask from a component
size
i965/nir/vec4: Implement loop statements (nir_cf_node_loop)
i965/nir/vec4: Implement load_input intrinsic
i965/nir/vec4: Implement store_output intrinsic
i965: Take is_scalar_shader_stage() method out to allow reuse
i965/nir/vec4: Implement nir_emit_jump
i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()
i965/vec4: Move is_high_sample() method to vec4_visitor class
i965/nir/vec4: Add utility method shader_opcode_for_nir_opcode()
i965/nir/vec4: Add nir_swizzle_result() method to vec4_visitor
i965/nir/vec4: Implement nir_tex_src_ddx and nir_tex_src_ddy tex
sources
i965/nir/vec4: Implement nir_tex_src_offset tex source
i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse
i965/nir/vec4: Implement nir_tex_src_sampler_offset tex source
i965/nir/vec4: Implement nir_tex_src_ms_index tex source
i965/nir/vec4: Implement nir_texop_txs and nir_texop_query_levels
texture ops
i965/nir/vec4: Implement nir_texop_txf_ms texture op
i965/nir/vec4: Implement nir_texop_txd texture op
i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse
Iago Toral Quiroga (4):
i965/nir/vec4: Add setup of uniform variables
i965/nir/vec4: Implement conditional statements (nir_cf_node_if)
nir/nir_lower_io: Add vec4 support
i965/nir/vec4: Implement load_uniform intrinsic
Samuel Iglesias Gonsalvez (3):
i965/nir/vec4: Add nir_get_dst() and nir_get_src() methods
i965/nir/vec4: Implement nir_texop_tg4 texture op
nir: Fix output swizzle in get_mul_for_src
src/glsl/nir/nir.h | 18 +-
src/glsl/nir/nir_lower_io.c | 87 +-
src/glsl/nir/nir_opt_peephole_ffma.c | 5 +-
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 34 +-
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 2 +
src/mesa/drivers/dri/i965/brw_nir.c | 78 +-
src/mesa/drivers/dri/i965/brw_nir.h | 5 +
src/mesa/drivers/dri/i965/brw_program.c | 5 +
src/mesa/drivers/dri/i965/brw_reg.h | 9 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 36 +-
src/mesa/drivers/dri/i965/brw_shader.h | 13 +
src/mesa/drivers/dri/i965/brw_vec4.cpp | 49 +-
src/mesa/drivers/dri/i965/brw_vec4.h | 65 +-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 7 +-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h | 3 +-
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 1710 +++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 65 +-
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 5 +-
src/mesa/drivers/dri/i965/brw_vs.h | 3 +-
20 files changed, 2063 insertions(+), 137 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
--
2.1.4
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