[Mesa-dev] [PATCH 72/78] i965/nir/vec4: Implement nir_texop_txs and nir_texop_query_levels texture ops

[Eduardo Lima Mitev]

The implementation is taken as-is from vec4_visitor.

It is similar for both operations, so it makes sense to group them together.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 92c88d4..b1c6659 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1574,7 +1574,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
    int param_base = inst->base_mrf + inst->header_size;
 
    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
-      /* @TODO: not yet implemented */
+      emit(MOV(dst_reg(MRF, param_base, lod.type, WRITEMASK_X), lod));
    } else {
       /* Load the coordinate */
       int coord_mask = (1 << instr->coord_components) - 1;
@@ -1627,6 +1627,18 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
    /* Emit the instruction */
    emit(inst);
 
+   /* fixup num layers (z) for cube arrays: hardware returns faces * layers;
+    * spec requires layers.
+    */
+   if (instr->op == nir_texop_txs) {
+      if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
+          instr->is_array) {
+         emit_math(SHADER_OPCODE_INT_QUOTIENT,
+                   writemask(inst->dst, WRITEMASK_Z),
+                   src_reg(inst->dst), src_reg(6));
+      }
+   }
+
    /* Move the result to the destination registry, applying swizzle */
    dst_reg dest = get_nir_dest(instr->dest, brw_type_for_base_type(dest_type));
 
-- 
2.1.4