[Mesa-dev] [PATCH] i965/gen9: Use custom MOCS entries set up by the kernel.

[Ben Widawsky]

On Tue, Jun 30, 2015 at 11:25:42PM +0300, Francisco Jerez wrote:
> Instead of relying on hardware defaults the i915 kernel driver is
> going program custom MOCS tables system-wide on Gen9 hardware.  The
> "WT" entry previously used for renderbuffers had a number of problems:
> It disabled caching on eLLC, it used a reserved L3 cacheability
> setting, and it used to override the PTE controls making renderbuffers
> always WT on LLC regardless of the kernel's setting.  Instead use an
> entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,
> L3CC=WB.
> 
> Even though the corresponding kernel change is in a way an ABI break
> it doesn't seem necessary to check that the kernel is recent enough
> because the change should only affect Gen9 which is still unreleased
> hardware.

I think the commit message is a bit confusing. You correctly mention the WT->PTE
fix, but then the reasoning for the WB change isn't clear [to me].

In any case, I think it makes a lot more sense to fix the PTE setting as one
patch for the old table, then a patch to update both WB and WT to the new table
settings. Also, we do have customers (Canonical) that want to make this work on
mesa 10.5, and with an older kernel. Therefore I think the two separate patches,
and doing it without the dependency on Ville's patch (which I like FWIW) make
the lives of everyone easiest. Then Ville can rebase his patch on top of this
for mesa 10.7 time.

I did think of it, but never broached the subject if we want to send both my
MOCS patch, and the PTE version of this patch to stable.

Anyway, the concept here is definitely
Acked-by: Ben Widawsky <ben at bwidawsk.net>

> ---
> Note that this change is based on Ville's "[PATCH 1/2] i965: House
> MOCS settings in brw_context/brw_device_info":
> 
> http://lists.freedesktop.org/archives/mesa-dev/2015-June/086665.html

Could you include a reference to the kernel patch too if you end up resending?

> 
>  src/mesa/drivers/dri/i965/brw_defines.h     | 16 +++++++++++-----
>  src/mesa/drivers/dri/i965/brw_device_info.c |  5 +++--
>  2 files changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
> index 497da9c..2889118 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -2499,12 +2499,18 @@ enum brw_wm_barycentric_interp_mode {
>   */
>  #define CHV_MOCS_L3	0x78
>  
> -/* Skylake: MOCS is now an index into an array of 64 different configurable
> - * cache settings.  We still use only either write-back or write-through; and
> - * rely on the documented default values.
> +/* Skylake: MOCS is now an index into an array of 64 different caching
> + * configurations programmed by the kernel.
>   */
> -#define SKL_MOCS_WB (0b001001 << 1)
> -#define SKL_MOCS_WT (0b000101 << 1)
> +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
> +#define SKL_MOCS_WB  (1 << 1)
> +/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
> +#define SKL_MOCS_PTE (9 << 1)
> +
> +/* Broxton: As for Skylake this should match the tables set up by the kernel.
> + */
> +/* L3CC=WB */
> +#define BXT_MOCS_L3  (9 << 1)
>  
>  #define MEDIA_VFE_STATE                         0x7000
>  /* GEN7 DW2, GEN8+ DW3 */
> diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
> index 167ecb5..d5133e0 100644
> --- a/src/mesa/drivers/dri/i965/brw_device_info.c
> +++ b/src/mesa/drivers/dri/i965/brw_device_info.c
> @@ -305,7 +305,6 @@ static const struct brw_device_info brw_device_info_chv = {
>  };
>  
>  /* Thread counts and URB limits are placeholders, and may not be accurate. */
> -/* FINISHME: Use PTE MOCS on Skylake. */
>  #define GEN9_FEATURES                               \
>     .gen = 9,                                        \
>     .has_hiz_and_separate_stencil = true,            \
> @@ -315,7 +314,7 @@ static const struct brw_device_info brw_device_info_chv = {
>     .max_vs_threads = 280,                           \
>     .max_gs_threads = 256,                           \
>     .max_wm_threads = 408,                           \
> -   .mocs_pte = SKL_MOCS_WT,                         \
> +   .mocs_pte = SKL_MOCS_PTE,                        \
>     .mocs_wb = SKL_MOCS_WB,                          \
>     .urb = {                                         \
>        .size = 128,                                  \
> @@ -352,6 +351,8 @@ static const struct brw_device_info brw_device_info_bxt = {
>     .max_vs_threads = 112,
>     .max_gs_threads = 112,
>     .max_wm_threads = 32,
> +   .mocs_pte = BXT_MOCS_L3,
> +   .mocs_wb = BXT_MOCS_L3,
>     .urb = {
>        .size = 64,
>        .min_vs_entries = 34,
> -- 
> 2.4.3
> 
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-- 
Ben Widawsky, Intel Open Source Technology Center