[Mesa-dev] [PATCH 22/23] i965/gen9: Enable the use of YF/YS tiling on skl+

[Anuj Phogat]

Note: Buffer size condition used in this patch to choose between
YF / YS tiling is just a place holder. I need some suggestions
here.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 79 ++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index ce954dd..b563e12 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -684,6 +684,72 @@ intel_miptree_total_width_height(struct brw_context *brw,
    }
 }
 
+static bool
+intel_miptree_choose_tr_mode(struct brw_context *brw,
+                             mesa_format format,
+                             uint32_t width0,
+                             uint32_t num_samples,
+                             enum intel_miptree_tiling_mode requested,
+                             struct intel_mipmap_tree *mt,
+                             uint32_t tr_mode)
+{
+   const unsigned bpp = mt->cpp * 8;
+   uint64_t size;
+   char *tr_mode_str;
+
+   /* bpp must be power of 2. */
+   if (!mt->compressed &&
+       _mesa_is_format_color_format(mt->format) &&
+       (requested == INTEL_MIPTREE_TILING_Y ||
+        requested == INTEL_MIPTREE_TILING_ANY) &&
+       (bpp && (bpp & (bpp - 1)) == 0)) {
+
+      mt->tr_mode = tr_mode;
+      mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt);
+      mt->align_h = intel_vertical_texture_alignment_unit(brw, mt);
+
+      intel_miptree_total_width_height(brw, mt);
+
+      tr_mode_str = mt->tr_mode == INTEL_MIPTREE_TRMODE_NONE ?
+                                   "INTEL_MIPTREE_TRMODE_NONE" :
+                                   (mt->tr_mode == INTEL_MIPTREE_TRMODE_YF ?
+                                    "INTEL_MIPTREE_TRMODE_YF" :
+                                    "INTEL_MIPTREE_TRMODE_YS");
+
+      mt->tiling = intel_miptree_choose_tiling(brw, format, width0,
+                                               num_samples,
+                                               requested, mt);
+
+      if (mt->tiling == I915_TILING_Y ||
+          mt->tiling == (I915_TILING_Y | I915_TILING_X)) {
+
+         size = mt->total_width * mt->total_height * mt->cpp;
+
+         /* Don't use YS tiling if buffer size is not the multiple of 64KB.
+          * Using 64KB format for buffers not meeting above condition will
+          * result in to wastage of memory.
+          *
+          * FIXME: Revisit this logic when we have more information about
+          * the specific cases when using YF/YS will be useful.
+          */
+         if ((mt->tr_mode == INTEL_MIPTREE_TRMODE_YS && size % 65536 == 0) ||
+             mt->tr_mode == INTEL_MIPTREE_TRMODE_YF)
+            return true;
+      }
+
+      /* Can't use requested tr_mode. Free up the memory allocated for
+       * miptree levels in intel_miptree_total_width_height().
+       */
+      unsigned level;
+      for (level = mt->first_level; level <= mt->last_level; level++) {
+         free(mt->level[level].slice);
+         mt->level[level].slice = NULL;
+      }
+   }
+
+   return false;
+}
+
 void
 brw_miptree_layout(struct brw_context *brw,
                    mesa_format format,
@@ -695,6 +761,19 @@ brw_miptree_layout(struct brw_context *brw,
 {
    bool gen6_hiz_or_stencil = false;
 
+   /* Check in advance if we can do Y tiling with Yf or Ys tiled resource
+    * modes. Fall back to using INTEL_MIPTREE_TRMODE_NONE.
+    */
+   if (brw->gen >= 9 && !for_bo) {
+      if (intel_miptree_choose_tr_mode(brw, format, width0, num_samples,
+                                       requested, mt,
+                                       INTEL_MIPTREE_TRMODE_YF) ||
+          intel_miptree_choose_tr_mode(brw, format, width0, num_samples,
+                                       requested, mt,
+                                       INTEL_MIPTREE_TRMODE_YS))
+         return;
+   }
+
    mt->tr_mode = INTEL_MIPTREE_TRMODE_NONE;
 
    if (brw->gen == 6 && mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
-- 
2.3.4