[Mesa-dev] [PATCH V2 21/23] i965/gen9: Use blitter as fallback path to read write YF/YS surfaces

[Anuj Phogat]

V2: Make relevant changes in intelTexSubImage().

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
 src/mesa/drivers/dri/i965/intel_pixel_read.c   |  7 -------
 src/mesa/drivers/dri/i965/intel_tex_image.c    | 15 ---------------
 src/mesa/drivers/dri/i965/intel_tex_subimage.c |  7 -------
 3 files changed, 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 4d256df..ee7a284 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -222,7 +222,6 @@ intelReadPixels(struct gl_context * ctx,
    struct brw_context *brw = brw_context(ctx);
    bool dirty;
    bool create_pbo = false;
-   uint32_t tr_mode = INTEL_MIPTREE_TRMODE_NONE;
 
    DBG("%s\n", __FUNCTION__);
 
@@ -233,7 +232,6 @@ intelReadPixels(struct gl_context * ctx,
          &readFb->Attachment[att_index];
       struct gl_renderbuffer *rb = readAtt->Renderbuffer;
       const struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-      tr_mode = irb->mt->tr_mode;
       create_pbo = irb->mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE;
    }
 
@@ -243,11 +241,6 @@ intelReadPixels(struct gl_context * ctx,
                                      pack))
       return;
 
-   /* Currently there are no fallback paths to read data from surfaces with
-    * tr_mode != INTEL_MIPTREE_TRMODE_NONE.
-    */
-   assert(tr_mode == INTEL_MIPTREE_TRMODE_NONE);
-
    if (_mesa_is_bufferobj(ctx->Pack.BufferObj))
       perf_debug("%s: fallback to CPU mapping in PBO case\n", __FUNCTION__);
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 8e845c6..838e07a 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -96,7 +96,6 @@ intelTexImage(struct gl_context * ctx,
    struct brw_context *brw = brw_context(ctx);
    bool ok;
    bool create_pbo = false;
-   uint32_t tr_mode = INTEL_MIPTREE_TRMODE_NONE;
    bool tex_busy = intelImage->mt && drm_intel_bo_busy(intelImage->mt->bo);
 
    DBG("%s mesa_format %s target %s format %s type %s level %d %dx%dx%d\n",
@@ -114,8 +113,6 @@ intelTexImage(struct gl_context * ctx,
    assert(intelImage->mt);
 
    if (brw->gen >= 9) {
-      tr_mode = intelImage->mt->tr_mode;
-
       /* Set create_pbo = true for surfaces with INTEL_MIPTREE_TRMODE_{YF/YS}.
        * _mesa_meta_pbo_TexSubImage() is the only working path to upload data
        * to such surfaces.
@@ -135,11 +132,6 @@ intelTexImage(struct gl_context * ctx,
    if (ok)
       return;
 
-   /* Currently there are no fallback paths to upload data to surfaces with
-    * tr_mode != INTEL_MIPTREE_TRMODE_NONE.
-    */
-   assert(tr_mode == INTEL_MIPTREE_TRMODE_NONE);
-
    ok = intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
                                        0, 0, 0, /*x,y,z offsets*/
                                        texImage->Width,
@@ -499,13 +491,11 @@ intel_get_tex_image(struct gl_context *ctx,
    struct brw_context *brw = brw_context(ctx);
    bool ok;
    bool create_pbo = false;
-   uint32_t tr_mode = INTEL_MIPTREE_TRMODE_NONE;
 
    DBG("%s\n", __FUNCTION__);
 
    if (brw->gen >= 9) {
       struct intel_texture_image *intelImage = intel_texture_image(texImage);
-      tr_mode = intelImage->mt->tr_mode;
       create_pbo = intelImage->mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE;
    }
 
@@ -516,11 +506,6 @@ intel_get_tex_image(struct gl_context *ctx,
                                      false /*for_readpixels*/, &ctx->Pack))
       return;
 
-   /* Currently there are no fallback paths to read data from surfaces with
-    * tr_mode != INTEL_MIPTREE_TRMODE_NONE.
-    */
-   assert(tr_mode == INTEL_MIPTREE_TRMODE_NONE);
-
    if (_mesa_is_bufferobj(ctx->Pack.BufferObj))
       perf_debug("%s: fallback to CPU mapping in PBO case\n", __FUNCTION__);
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index a7ad10e..6b3b78f 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -203,7 +203,6 @@ intelTexSubImage(struct gl_context * ctx,
    struct brw_context *brw = brw_context(ctx);
    bool ok;
    bool create_pbo = false;
-   uint32_t tr_mode = INTEL_MIPTREE_TRMODE_NONE;
    bool tex_busy = intelImage->mt && drm_intel_bo_busy(intelImage->mt->bo);
 
    DBG("%s mesa_format %s target %s format %s type %s level %d %dx%dx%d\n",
@@ -213,7 +212,6 @@ intelTexSubImage(struct gl_context * ctx,
        texImage->Level, texImage->Width, texImage->Height, texImage->Depth);
 
    if (brw->gen >= 9) {
-      tr_mode = intelImage->mt->tr_mode;
       /* Set create_pbo = true for surfaces with INTEL_MIPTREE_TRMODE_{YF/YS}.
        * _mesa_meta_pbo_TexSubImage() is the only working path to upload data
        * to such surfaces.
@@ -231,11 +229,6 @@ intelTexSubImage(struct gl_context * ctx,
    if (ok)
       return;
 
-   /* Currently there are no fallback paths to upload data to surfaces with
-    * tr_mode != INTEL_MIPTREE_TRMODE_NONE.
-    */
-   assert(tr_mode == INTEL_MIPTREE_TRMODE_NONE);
-
    ok = intel_texsubimage_tiled_memcpy(ctx, dims, texImage,
                                        xoffset, yoffset, zoffset,
                                        width, height, depth,
-- 
2.3.4