[Mesa-dev] [PATCH 6/7] i965: Pass slice details as parameters for surface setup
Francisco Jerez
currojerez at riseup.net
Thu May 7 07:15:40 PDT 2015
From: Topi Pohjolainen <topi.pohjolainen at intel.com>
Also changed a couple of direct shifts into SET_FIELD().
Fixes: arb_copy_image-formats -auto -fbo on ILK. In principle,
minimum level settings are only for TextureView to use. We,
however, also take advantage of that internally when blitting.
Before this patch this wasn't taken into account for ILK in the
surface setup.
v2:
- Removed extra whitespace and switched tabs to spaces (Matt)
- Added assertion on minimum level (Ken).
v3 (Curro): Reorder min_layer and effective_depth
Reviewed-by: Matt Turner <mattst88 at gmail.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
[ Francisco Jerez: Non-trivial rebase. Pass a half-open interval of
levels like emit_texture_surface_state does. ]
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
---
src/mesa/drivers/dri/i965/brw_context.h | 3 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 31 +++++++++++++++--------
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 10 +++-----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 11 +++-----
4 files changed, 30 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 6f08b06..2eb4251 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -985,10 +985,11 @@ struct brw_context
{
void (*update_texture_surface)(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj,
GLenum target,
unsigned min_layer,
unsigned max_layer,
+ unsigned min_level,
+ unsigned max_level,
uint32_t tex_format, unsigned swizzle,
uint32_t *surf_offset,
bool for_gather);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index fa4e36d..de4bdc5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -310,14 +310,15 @@ update_buffer_texture_surface(struct gl_context *ctx,
static void
brw_update_texture_surface(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- struct gl_texture_object *tObj, GLenum target,
+ GLenum target,
unsigned min_layer /* unused */,
unsigned max_layer /* unused */,
+ unsigned min_level,
+ unsigned max_level,
uint32_t tex_format, unsigned swizzle /* unused */,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intelObj = intel_texture_object(tObj);
uint32_t *surf;
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
@@ -359,16 +360,16 @@ brw_update_texture_surface(struct brw_context *brw,
surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
- surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
- (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
- (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
+ surf[2] = SET_FIELD(max_level - min_level - 1, BRW_SURFACE_LOD) |
+ SET_FIELD(mt->logical_width0 - 1, BRW_SURFACE_WIDTH) |
+ SET_FIELD(mt->logical_height0 - 1, BRW_SURFACE_HEIGHT);
- surf[3] = (brw_get_surface_tiling_bits(mt->tiling) |
- (mt->logical_depth0 - 1) << BRW_SURFACE_DEPTH_SHIFT |
- (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ surf[3] = brw_get_surface_tiling_bits(mt->tiling) |
+ SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) |
+ SET_FIELD(mt->pitch - 1, BRW_SURFACE_PITCH);
- surf[4] = (brw_get_surface_num_multisamples(mt->num_samples) |
- SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
+ surf[4] = brw_get_surface_num_multisamples(mt->num_samples) |
+ SET_FIELD(min_level - mt->first_level, BRW_SURFACE_MIN_LOD);
surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
@@ -827,8 +828,16 @@ update_texture_surface(struct gl_context *ctx,
format = BRW_SURFACEFORMAT_R8_UINT;
}
- brw->vtbl.update_texture_surface(brw, mt, obj, obj->Target,
+ /* Minimum level is only supported for TextureView but internally it is
+ * also taken advantage of by meta blit path. The former is only enabled
+ * from gen7 onwards.
+ */
+ assert(brw->gen >= 7 || obj->MinLevel == 0 || brw->meta_in_progress);
+
+ brw->vtbl.update_texture_surface(brw, mt, obj->Target,
obj->MinLayer, obj->MinLayer + depth,
+ obj->MinLevel + obj->BaseLevel,
+ obj->MinLevel + intel_obj->_MaxLevel + 1,
format, swizzle, surf_offset, for_gather);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 89dba40..61e8423 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -350,21 +350,19 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
static void
gen7_update_texture_surface(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- struct gl_texture_object *obj, GLenum target,
- unsigned min_layer,
- unsigned max_layer,
+ GLenum target,
+ unsigned min_layer, unsigned max_layer,
+ unsigned min_level, unsigned max_level,
uint32_t tex_format, unsigned swizzle,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intel_obj = intel_texture_object(obj);
if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT)
tex_format = BRW_SURFACEFORMAT_R32G32_FLOAT_LD;
gen7_emit_texture_surface_state(brw, mt, target,
min_layer, max_layer,
- obj->MinLevel + obj->BaseLevel,
- obj->MinLevel + intel_obj->_MaxLevel + 1,
+ min_level, max_level,
tex_format, swizzle,
surf_offset, false, for_gather);
}
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 9858f5f..129f141 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -249,19 +249,16 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
static void
gen8_update_texture_surface(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- struct gl_texture_object *obj, GLenum target,
- unsigned min_layer,
- unsigned max_layer,
+ GLenum target,
+ unsigned min_layer, unsigned max_layer,
+ unsigned min_level, unsigned max_level,
uint32_t tex_format, unsigned swizzle,
uint32_t *surf_offset,
bool for_gather)
{
- struct intel_texture_object *intel_obj = intel_texture_object(obj);
-
gen8_emit_texture_surface_state(brw, mt, target,
min_layer, max_layer,
- obj->MinLevel + obj->BaseLevel,
- obj->MinLevel + intel_obj->_MaxLevel + 1,
+ min_level, max_level,
tex_format, swizzle, surf_offset,
false, for_gather);
}
--
2.3.5
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