[Mesa-dev] [PATCH] i965: Fix texture views of 2d array surfaces

[Ben Widawsky]

On Mon, Nov 02, 2015 at 12:05:32PM -0800, Ben Widawsky wrote:
> It is legal to have a texture view of a single layer from a 2D array texture;
> you can sample from it, or render to it. Intel hardware needs to be made aware
> when it is using a 2d array surface in the surface state. The texture view is
> just a 2d surface with the backing miptree actually being a 2d array surface.
> This caused the previous code would not set the right bit in the surface state
> since it wasn't considered an array texture.
> 
> I spotted this early on in debug but brushed it off because it is clearly not
> needed on other platforms (since they all pass). I have no idea how this works
> properly on other platforms (I think gen7 introduced the bit in the state, but I
> am too lazy to check). As such, I have opted not to modify gen7, though I
> believe the current code is wrong there as well.
> 
> Thanks to Chris for helping me debug this.
> 
> Cc: Chris Forbes <chrisf at ijw.co.nz>
> Reported-by: Mark Janes <mark.a.janes at intel.com> (Jenkins)
> References: https://www.opengl.org/registry/specs/ARB/texture_view.txt
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen8_surface_state.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 18b8665..19d449b 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -252,8 +252,9 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
>          format == BRW_SURFACEFORMAT_BC7_UNORM))
>        surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
>  
> -   if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
> +   if (depth && target != GL_TEXTURE_3D) {
>        surf[0] |= GEN8_SURFACE_IS_ARRAY;
> +   }

Something isn't right here. I think it should be depth > 1, but when I change
that the test fails. I need to think about this some more I guess.

>  
>     surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
>  
> @@ -428,7 +429,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>     case GL_TEXTURE_CUBE_MAP_ARRAY:
>     case GL_TEXTURE_CUBE_MAP:
>        surf_type = BRW_SURFACE_2D;
> -      is_array = true;
>        depth *= 6;
>        break;
>     case GL_TEXTURE_3D:
> @@ -436,10 +436,11 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>        /* fallthrough */
>     default:
>        surf_type = translate_tex_target(gl_target);
> -      is_array = _mesa_tex_target_is_array(gl_target);
>        break;
>     }
>  
> +   is_array = depth > 1 && gl_target != GL_TEXTURE_3D;
> +
>     /* _NEW_BUFFERS */
>     /* Render targets can't use IMS layout. Stencil in turn gets configured as
>      * single sampled and indexed manually by the program.
> -- 
> 2.6.1
> 
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