[Mesa-dev] [PATCH 01/13] i965/shader: Pull assign_common_binding_table_offsets out of backend_shader
Jason Ekstrand
jason at jlekstrand.net
Thu Oct 1 18:50:27 PDT 2015
This really has nothing to do with the backend compiler and we'd like to
eventually be able to set this up earlier in the compile process.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 12 +++++++++---
src/mesa/drivers/dri/i965/brw_shader.cpp | 17 +++++++++++++----
src/mesa/drivers/dri/i965/brw_shader.h | 11 +++++++++--
src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 ++-
src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp | 4 +++-
5 files changed, 36 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b062219..e90151b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4749,7 +4749,9 @@ fs_visitor::assign_fs_binding_table_offsets()
prog_data->binding_table.render_target_start = next_binding_table_offset;
next_binding_table_offset += MAX2(key->nr_color_regions, 1);
- assign_common_binding_table_offsets(next_binding_table_offset);
+ brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo,
+ shader_prog, prog, stage_prog_data,
+ next_binding_table_offset);
}
void
@@ -4763,7 +4765,9 @@ fs_visitor::assign_cs_binding_table_offsets()
prog_data->binding_table.work_groups_start = next_binding_table_offset;
next_binding_table_offset++;
- assign_common_binding_table_offsets(next_binding_table_offset);
+ brw_assign_common_binding_table_offsets(MESA_SHADER_COMPUTE, devinfo,
+ shader_prog, prog, stage_prog_data,
+ next_binding_table_offset);
}
void
@@ -4979,7 +4983,9 @@ fs_visitor::run_vs(gl_clip_plane *clip_planes)
{
assert(stage == MESA_SHADER_VERTEX);
- assign_common_binding_table_offsets(0);
+ brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX, devinfo,
+ shader_prog, prog, stage_prog_data,
+ 0);
setup_vs_payload();
if (shader_time_index >= 0)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 1d184a7..7c6043d 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1363,16 +1363,25 @@ backend_shader::invalidate_cfg()
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
void
-backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
+brw_assign_common_binding_table_offsets(gl_shader_stage stage,
+ const struct brw_device_info *devinfo,
+ const struct gl_shader_program *shader_prog,
+ const struct gl_program *prog,
+ struct brw_stage_prog_data *stage_prog_data,
+ uint32_t next_binding_table_offset)
{
+ const struct gl_shader *shader = NULL;
int num_textures = _mesa_fls(prog->SamplersUsed);
+ if (shader_prog)
+ shader = shader_prog->_LinkedShaders[stage];
+
stage_prog_data->binding_table.texture_start = next_binding_table_offset;
next_binding_table_offset += num_textures;
if (shader) {
stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
- next_binding_table_offset += shader->base.NumUniformBlocks;
+ next_binding_table_offset += shader->NumUniformBlocks;
} else {
stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
}
@@ -1403,9 +1412,9 @@ backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_
stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
}
- if (shader && shader->base.NumImages) {
+ if (shader && shader->NumImages) {
stage_prog_data->binding_table.image_start = next_binding_table_offset;
- next_binding_table_offset += shader->base.NumImages;
+ next_binding_table_offset += shader->NumImages;
} else {
stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index eeb3306..9690332 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -24,6 +24,7 @@
#include <stdint.h>
#include "brw_reg.h"
#include "brw_defines.h"
+#include "brw_context.h"
#include "main/compiler.h"
#include "glsl/ir.h"
#include "program/prog_parameter.h"
@@ -266,8 +267,6 @@ public:
void calculate_cfg();
void invalidate_cfg();
- void assign_common_binding_table_offsets(uint32_t next_binding_table_offset);
-
virtual void invalidate_live_intervals() = 0;
};
@@ -295,6 +294,14 @@ extern "C" {
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
+void
+brw_assign_common_binding_table_offsets(gl_shader_stage stage,
+ const struct brw_device_info *devinfo,
+ const struct gl_shader_program *shader_prog,
+ const struct gl_program *prog,
+ struct brw_stage_prog_data *stage_prog_data,
+ uint32_t next_binding_table_offset);
+
bool brw_vs_precompile(struct gl_context *ctx,
struct gl_shader_program *shader_prog,
struct gl_program *prog);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 4e9f3f7..0072998 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1711,7 +1711,8 @@ vec4_vs_visitor::setup_payload(void)
void
vec4_visitor::assign_binding_table_offsets()
{
- assign_common_binding_table_offsets(0);
+ brw_assign_common_binding_table_offsets(stage, devinfo, shader_prog, prog,
+ stage_prog_data, 0);
}
src_reg
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
index 6db6d27..5219007 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
@@ -41,7 +41,9 @@ gen6_gs_visitor::assign_binding_table_offsets()
/* In gen6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform
* feedback surfaces.
*/
- assign_common_binding_table_offsets(BRW_MAX_SOL_BINDINGS);
+ brw_assign_common_binding_table_offsets(MESA_SHADER_GEOMETRY, devinfo,
+ shader_prog, prog, stage_prog_data,
+ BRW_MAX_SOL_BINDINGS);
}
void
--
2.5.0.400.gff86faf
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