[Mesa-dev] [PATCH 1/2] radeonsi: remove TC L2 cache flush for index buffers on VI

[Alex Deucher]

On Wed, Oct 7, 2015 at 12:54 PM, Marek Olšák <maraeo at gmail.com> wrote:
> Ping
>

For the series:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> On Sat, Oct 3, 2015 at 7:55 PM, Marek Olšák <maraeo at gmail.com> wrote:
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> ---
>>  src/gallium/drivers/radeonsi/si_state_draw.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
>> index 43170ec..5face42 100644
>> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
>> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
>> @@ -813,9 +813,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
>>                 }
>>         }
>>
>> -       /* TODO: VI should read index buffers through TC, so this shouldn't be
>> -        * needed on VI. */
>> -       if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
>> +       /* VI reads index buffers through TC L2. */
>> +       if (info->indexed && sctx->b.chip_class <= CIK &&
>> +           r600_resource(ib.buffer)->TC_L2_dirty) {
>>                 sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
>>                 r600_resource(ib.buffer)->TC_L2_dirty = false;
>>         }
>> --
>> 2.1.4
>>
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