[Mesa-dev] [PATCH] i965/vec4: Implement b2f and b2i using negation.
imirkin at alum.mit.edu
Sun Oct 11 18:27:27 PDT 2015
On Sun, Oct 11, 2015 at 9:25 PM, Matt Turner <mattst88 at gmail.com> wrote:
> On Sun, Oct 11, 2015 at 5:26 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
>> On Sat, Oct 10, 2015 at 1:17 PM, Matt Turner <mattst88 at gmail.com> wrote:
>>> Curro added this in commit 3ee2daf23d (before the vec4/NIR backend was
>>> added) but it was missed in the new NIR backend. Add it there as well.
>>> instructions in affected programs: 1857 -> 1810 (-2.53%)
>>> helped: 15
>>> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +-------
>>> 1 file changed, 1 insertion(+), 7 deletions(-)
>>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>>> index 41bd80d..fdf767d 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>>> @@ -1237,14 +1237,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>>> case nir_op_b2i:
>>> - emit(AND(dst, op, src_reg(1)));
>>> - break;
>>> case nir_op_b2f:
>>> - op.type = BRW_REGISTER_TYPE_D;
>>> - dst.type = BRW_REGISTER_TYPE_D;
>>> - emit(AND(dst, op, src_reg(0x3f800000u)));
>>> - dst.type = BRW_REGISTER_TYPE_F;
>>> + emit(MOV(dst, negate(op)));
>> For my own edification, could you explain how this works? Let's say
>> you have a sequence like...
>> bool b = ...; /* b contains 0 or ~0 "internally" */
>> int x = floatBitsToInt((float)b) + 1;
> b2f generates a type-converting MOV: mov dst:F, -src0:D.
Aha, this is the bit that I was missing. That makes sense then.
> Input of 0 is 0 negated, and 0.0f. Input of ~0 (-1) is 1 negated, and 1.0f.
> Your sequence would generate
> mov r0:F, -r1:D
> add r2:D, r0:D, 1
> and copy propagation won't mess things up because it only operates on
> mixed-types in known-safe cases.
> (I haven't confirmed this)
If that were broken, probably a lot more things would be broken.
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