[Mesa-dev] [PATCH v2 07/11] i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.
Kenneth Graunke
kenneth at whitecape.org
Mon Oct 12 14:49:09 PDT 2015
This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs,
which controls whether or not to use SIMD8 geometry shaders.
For now, we control it via a new environment variable, INTEL_SCALAR_GS.
This provides a convenient way to try it out.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_gs.c | 3 ++-
src/mesa/drivers/dri/i965/brw_shader.cpp | 5 +++++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index e0165fb..1ae9763 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -57,6 +57,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
struct brw_geometry_program *gp,
struct brw_gs_prog_key *key)
{
+ struct brw_compiler *compiler = brw->intelScreen->compiler;
struct brw_stage_state *stage_state = &brw->gs.base;
struct brw_gs_compile c;
memset(&c, 0, sizeof(c));
@@ -92,7 +93,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
c.prog_data.base.base.nr_image_params = gs->NumImages;
brw_nir_setup_glsl_uniforms(gp->program.Base.nir, prog, &gp->program.Base,
- &c.prog_data.base.base, false);
+ &c.prog_data.base.base, compiler->scalar_gs);
if (brw->gen >= 8) {
c.prog_data.static_vertex_count = !gp->program.Base.nir ? -1 :
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 42b9969..242219a 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -79,6 +79,8 @@ is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
case MESA_SHADER_FRAGMENT:
case MESA_SHADER_COMPUTE:
return true;
+ case MESA_SHADER_GEOMETRY:
+ return compiler->scalar_gs;
case MESA_SHADER_VERTEX:
return compiler->scalar_vs;
default:
@@ -101,6 +103,9 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
compiler->scalar_vs = true;
+ if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
+ compiler->scalar_gs = true;
+
nir_shader_compiler_options *nir_options =
rzalloc(compiler, nir_shader_compiler_options);
nir_options->native_integers = true;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index ad2de5e..4ef8c96 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -93,6 +93,7 @@ struct brw_compiler {
void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
bool scalar_vs;
+ bool scalar_gs;
struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
};
--
2.6.1
More information about the mesa-dev
mailing list