[Mesa-dev] [PATCH 13/16] nvc0: enable compute support by default on Fermi
imirkin at alum.mit.edu
Sat Oct 17 13:34:19 PDT 2015
On Sat, Oct 17, 2015 at 4:31 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> On Sat, Oct 17, 2015 at 4:24 PM, Jan Vesely <jan.vesely at rutgers.edu> wrote:
>> On Sat, 2015-10-17 at 15:24 -0400, Ilia Mirkin wrote:
>>> "compute" in this context is "initialize the compute engine so that
>>> kernels may be executed", not "convert the llvm ir bitcode that
>>> hands us into nv50 ir". The former has actually been around for
>>> Samuel just fixed up a few fermi-specific bits.
>> Can't we use LLVM IR-> TGSI -> nv IR for that?
> Sure, there's no LLVM IR -> TGSI conversion though.
BTW, Pierre Moreau is working on a SPIR-V -> nv50 ir adapter, which
will hopefully mean that once a SPIR-V llvm backend exists (such a
thing *is* in the plans by... someone, right?) that would be able to
be used. He hasn't made a lot of progress though.
Among other things, SPIR-V is SSA, and nv50 ir input has to be non-ssa
(because, among other things, the various lowering passes generate
non-ssa code, futz with control flow, etc).
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