[Mesa-dev] [PATCH 13/16] nvc0: enable compute support by default on Fermi
jan.vesely at rutgers.edu
Sun Oct 18 11:18:42 PDT 2015
On Sat, 2015-10-17 at 16:34 -0400, Ilia Mirkin wrote:
> On Sat, Oct 17, 2015 at 4:31 PM, Ilia Mirkin <imirkin at alum.mit.edu>
> > On Sat, Oct 17, 2015 at 4:24 PM, Jan Vesely <jan.vesely at rutgers.edu
> > > wrote:
> > > On Sat, 2015-10-17 at 15:24 -0400, Ilia Mirkin wrote:
> > > > "compute" in this context is "initialize the compute engine so
> > > > that
> > > > kernels may be executed", not "convert the llvm ir bitcode that
> > > > clover
> > > > hands us into nv50 ir". The former has actually been around for
> > > > years,
> > > > Samuel just fixed up a few fermi-specific bits.
> > >
> > > Can't we use LLVM IR-> TGSI -> nv IR for that?
> > Sure, there's no LLVM IR -> TGSI conversion though.
my bad, I assumed that since there is one in reverse direction, there
would be one in this direction as well.
> BTW, Pierre Moreau is working on a SPIR-V -> nv50 ir adapter, which
> will hopefully mean that once a SPIR-V llvm backend exists (such a
> thing *is* in the plans by... someone, right?) that would be able to
> be used. He hasn't made a lot of progress though.
> Among other things, SPIR-V is SSA, and nv50 ir input has to be non
> (because, among other things, the various lowering passes generate
> non-ssa code, futz with control flow, etc).
Yeah, SPIR-V makes more sense and looks like better investment.
thanks for all the answers,
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