[Mesa-dev] [PATCH 6/7] i965: Implement nir_intrinsic_shader_clock

[Connor Abbott]

On Mon, Oct 19, 2015 at 10:46 AM, Emil Velikov <emil.l.velikov at gmail.com> wrote:
> Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp   |  9 +++++++++
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 10 ++++++++++
>  2 files changed, 19 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index 792663f..0a28b05 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1309,6 +1309,15 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>        break;
>     }
>
> +   case nir_intrinsic_shader_clock: {
> +      /* We cannot do anything if there is an event, so ignore it for now */
> +      fs_reg shader_clock = get_timestamp(bld);
> +
> +      bld.MOV(retype(dest, brw_type_for_base_type(glsl_type::uvec2_type)),
> +              shader_clock);

This isn't correct. With your earlier patch, get_timestamp() now
returns a single SIMD4 register, whereas for shader_clock the
destination is a block of two contiguous SIMD8/16 registers, and you
need to fill them with the first two components of shader_clock using
LOAD_PAYLOAD. This is because a single NIR/GLSL scalar component
corresponds to a whole SIMD8/16 register in FS. For more details
(including some ASCII art that hopefully clarifies things), see my
response to your original patch:

http://lists.freedesktop.org/archives/mesa-dev/2015-October/096515.html

Actually, I think it's a little easier than that, though -- you can
just pass shader_clock.smear(0) and shader_clock.smear(1) as the
sources of your LOAD_PAYLOAD.

> +      break;
> +   }
> +
>     case nir_intrinsic_image_size: {
>        /* Get the referenced image variable and type. */
>        const nir_variable *var = instr->variables[0]->var;
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index ea1e3e7..36ec7ad 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -806,6 +806,16 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
>        break;
>     }
>
> +   case nir_intrinsic_shader_clock: {
> +      /* We cannot do anything if there is an event, so ignore it for now */
> +      src_reg shader_clock = get_timestamp();
> +      enum brw_reg_type type = brw_type_for_base_type(glsl_type::uvec2_type);
> +
> +      dest = get_nir_dest(instr->dest, type);
> +      emit(MOV(dest, retype(shader_clock, type)));
> +      break;
> +   }
> +
>     default:
>        unreachable("Unknown intrinsic");
>     }
> --
> 2.6.1
>
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