[Mesa-dev] [PATCH 1/4] i965/fs: Use type-W for immediate in SampleID setup.

[Anuj Phogat]

On Wed, Oct 21, 2015 at 10:05 AM, Matt Turner <mattst88 at gmail.com> wrote:
> Not a functional difference, but register is loaded with a signed
> immediate (V) and added to a signed type (D) producing a signed result
> (D).
>
> Also change the type of g0 to allow for compaction.
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp           | 4 ++--
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 49323eb..f9c78df 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1273,7 +1273,7 @@ fs_visitor::emit_sampleid_setup()
>     if (key->compute_sample_id) {
>        fs_reg t1 = vgrf(glsl_type::int_type);
>        fs_reg t2 = vgrf(glsl_type::int_type);
> -      t2.type = BRW_REGISTER_TYPE_UW;
> +      t2.type = BRW_REGISTER_TYPE_W;
>
>        /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
>         * 8x multisampling, subspan 0 will represent sample N (where N
> @@ -1295,7 +1295,7 @@ fs_visitor::emit_sampleid_setup()
>         * subspan 1, and finally sample 1 of subspan 1.
>         */
>        abld.exec_all()
> -          .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
> +          .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
>                 fs_reg(0xc0));
>        abld.exec_all().SHR(t1, t1, fs_reg(5));
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 13c495c..9a5992e1 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -1429,7 +1429,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
>     brw_set_default_exec_size(p, BRW_EXECUTE_8);
>     brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>     brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> -   struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
> +   struct brw_reg reg = stride(src1, 1, 4, 0);
>     if (dispatch_width == 8) {
>        brw_ADD(p, dst, src0, reg);
>     } else if (dispatch_width == 16) {
> --
> 2.4.9
>

Verified the generated instructions on IVB. Series is:
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>